Tung Thanh Hoang

According to our database1, Tung Thanh Hoang authored at least 12 papers between 2009 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2016
A Data Layout Transformation (DLT) accelerator: Architectural support for data movement optimization in accelerated-centric heterogeneous systems.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
10x10: A Case Study in Highly-Programmable and Energy-Efficient Heterogeneous Federated Architecture.
SIGARCH Computer Architecture News, 2015

Fast support for unstructured data processing: the unified automata processor.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

Does arithmetic logic dominate data movement? a systematic comparison of energy-efficiency for FFT accelerators.
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

2014
Performance and energy limits of a processor-integrated FFT accelerator.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2014

2012
Data-Width-Driven Power Gating of Integer Arithmetic Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Viterbi Accelerator for Embedded Processor Datapaths.
Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012

2010
A High-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit.
IEEE Trans. on Circuits and Systems, 2010

Cyclic Redundancy Checking (CRC) Accelerator for the FlexCore Processor.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Design space exploration for an embedded processor with flexible datapath interconnect.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

2009
High-speed, energy-efficient 2-cycle Multiply-Accumulate architecture.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Double Throughput Multiply-Accumulate unit for FlexCore processor enhancements.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009


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