Uk-Rae Cho

According to our database¹, Uk-Rae Cho authored at least 10 papers between 2003 and 2005.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Links

On csauthors.net:

Bibliography

2005

A Low Jitter ADPLL for Mobile Applications.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2005

A High Resolution, Wide Range Digital Impedance Controller.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2005

A 1.2V multi Gb/s/pin memory interface circuits with high linearity and low mismatch.

[BibT_eX]

[DOI]

Tae-Hyoung Kim

Uk-Rae Cho

Hyun-Geun Byun

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A pseudo-differential CMOS receiver insensitive to input common mode level.

[BibT_eX]

[DOI]

Nam-Seog Kim

Uk-Rae Cho

Hyun-Geun Byun

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Low voltage wide range DLL-based quad-phase core clock generator for high speed network SRAM application.

[BibT_eX]

[DOI]

Nam-Seog Kim

Uk-Rae Cho

Hyun-Geun Byun

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004

Synchronous mirror delay for multiphase locking.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2004

Modeling and Testing of Faults in TCAMs.

[BibT_eX]

[DOI]

Proceedings of the Systems Modeling and Simulation: Theory and Applications, 2004

2003

A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2003

New dynamic logic-level converters for high performance application.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Programmable and automatically adjustable on-die terminator for DDR3-SRAM interface.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

Uk-Rae Cho

Timeline

Legend:

Links

On csauthors.net:

Bibliography

Loading...