Hyun-Geun Byun

According to our database1, Hyun-Geun Byun authored at least 16 papers between 2003 and 2008.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2008
A 100nm Double-Stacked 500MHz 72Mb Separate-I/O Synchronous SRAM with Automatic Cell-Bias Scheme and Adaptive Block Redundancy.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
A 0.1-µm 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation.
IEEE J. Solid State Circuits, 2007

2006
An autonomous SRAM with on-chip sensors in an 80-nm double stacked cell technology.
IEEE J. Solid State Circuits, 2006

Enhanced write performance of a 64-mb phase-change random access memory.
IEEE J. Solid State Circuits, 2006


2005
A 0.18-μm 3.0-V 64-Mb nonvolatile phase-transition random access memory (PRAM).
IEEE J. Solid State Circuits, 2005

A Low Jitter ADPLL for Mobile Applications.
IEICE Trans. Electron., 2005

A High Resolution, Wide Range Digital Impedance Controller.
IEICE Trans. Electron., 2005

A 1.2V multi Gb/s/pin memory interface circuits with high linearity and low mismatch.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A pseudo-differential CMOS receiver insensitive to input common mode level.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Low voltage wide range DLL-based quad-phase core clock generator for high speed network SRAM application.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
Synchronous mirror delay for multiphase locking.
IEEE J. Solid State Circuits, 2004

Modeling and Testing of Faults in TCAMs.
Proceedings of the Systems Modeling and Simulation: Theory and Applications, 2004

2003
A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM.
IEEE J. Solid State Circuits, 2003

New dynamic logic-level converters for high performance application.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Programmable and automatically adjustable on-die terminator for DDR3-SRAM interface.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003


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