Nam-Seog Kim

Orcid: 0000-0002-1039-5945

According to our database1, Nam-Seog Kim authored at least 22 papers between 2003 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
A 2.4 GHz Wide-Range CMOS Current-Mode Class-D PA with HD2 Suppression for Internet of Things Applications.
Sensors, March, 2024

A Compact Model for Interface-Type Self-Rectifying Resistive Memory With Experiment Verification.
IEEE Access, 2024

2022
A 10-Bit, 600 MS/s Multi-Mode Direct-Sampling DAC-Based Transmitter.
IEEE Access, 2022

2021
A Spurious and Oscillator Pulling Free CMOS Quadrature LO-Generator for Cellular NB-IoT.
IEEE Trans. Very Large Scale Integr. Syst., 2021

2018
A Dual-Resolution Wavelet-Based Energy Detection Spectrum Sensing for UWB-Based Cognitive Radios.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A 0.46-2.1 GHz Spurious and Oscillator-Pulling Free LO Generator for Cellular NB-IoT Transmitter with 23 dBm Integrated PAs in 28nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
A 14-nm 0.14-ps<sub>rms</sub> Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration.
IEEE J. Solid State Circuits, 2017

24.8 A 14nm fractional-N digital PLL with 0.14psrms jitter and -78dBc fractional spur for cellular RFICs.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
A High Data-Rate Energy-Efficient Triple-Channel UWB-Based Cognitive Radio.
IEEE J. Solid State Circuits, 2016

A knowledge based freight management decision support system incorporating economies of scale: multimodal minimum cost flow optimization approach.
Inf. Technol. Manag., 2016

2015
A 1Gb/s energy efficient triple-channel UWB-based cognitive radio.
Proceedings of the Symposium on VLSI Circuits, 2015

A 3.1-10.6GHz wavelet-based dual-resolution spectrum sensing with harmonic rejection mixers.
Proceedings of the ESSCIRC Conference 2015, 2015

2014
An Energy-Efficient Triple-Channel UWB-based Cognitive Radio.
PhD thesis, 2014

2010
8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology.
IEEE J. Solid State Circuits, 2010

2009

2008
Multi-mode sub-Nyquist rate digital-to-analog conversion for direct waveform synthesis.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

2005
A pseudo-differential CMOS receiver insensitive to input common mode level.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Low voltage wide range DLL-based quad-phase core clock generator for high speed network SRAM application.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
Synchronous mirror delay for multiphase locking.
IEEE J. Solid State Circuits, 2004

2003
A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM.
IEEE J. Solid State Circuits, 2003

New dynamic logic-level converters for high performance application.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Programmable and automatically adjustable on-die terminator for DDR3-SRAM interface.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003


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