Vasileios Titopoulos
Orcid: 0009-0009-0123-5737
  According to our database1,
  Vasileios Titopoulos
  authored at least 9 papers
  between 2024 and 2025.
  
  
Collaborative distances:
Collaborative distances:
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Bibliography
  2025
    CoRR, July, 2025
    
  
    IEEE Trans. Computers, April, 2025
    
  
    Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2025
    
  
Low-Cost FlashAttention with Fused Exponential and Multiplication Hardware Operators.
    
  
    Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2025
    
  
Register Dispersion: Reducing the Footprint of the Vector Register File in Vector Engines of Low-Cost RISC-V CPUs.
    
  
    Proceedings of the 22nd ACM International Conference on Computing Frontiers, 2025
    
  
  2024
DeMM: A Decoupled Matrix Multiplication Engine Supporting Relaxed Structured Sparsity.
    
  
    IEEE Comput. Archit. Lett., 2024
    
  
A High-Level Synthesis Library for Synthesizing Efficient and Functional-Safe CNN Dataflow Accelerators.
    
  
    IEEE Access, 2024
    
  
IndexMAC: A Custom RISC-V Vector Instruction to Accelerate Structured-Sparse Matrix Multiplications.
    
  
    Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024