Vazgen Melikyan

According to our database1, Vazgen Melikyan authored at least 44 papers between 2008 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
Smart Adjustment Of Transistor Parameters To Reduce Temperature Rise Due To Self-Heating Effect.
Proceedings of the IEEE East-West Design & Test Symposium, 2023

Physical Design of 6T Cell of SRAM Devices and Comparative Analysis of Layout.
Proceedings of the IEEE East-West Design & Test Symposium, 2023

Tuning Genetic Algorithm Parameters for Placement of Integrated Circuit Cells.
Proceedings of the IEEE East-West Design & Test Symposium, 2023

Accelerating CNN Models for Visual Odometry: Design and FPGA Implementation for Efficient Hardware Acceleration.
Proceedings of the IEEE East-West Design & Test Symposium, 2023

2021
Enhanced pin-access prediction and design optimization with machine learning integration.
Microelectron. J., 2021

Design and Verification of Novel Sync Cell.
Proceedings of the IEEE East-West Design & Test Symposium, 2021

UVM Verification IP for AXI.
Proceedings of the IEEE East-West Design & Test Symposium, 2021

2019
Development of Method for Automation of SPICE Models Generation.
Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019

Power Supply Noise Rejection Improvement Method in Modern VLSI Design.
Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019

Unit Regression Test Selection Mechanism Based on Hashing Algorithm.
Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019

2018
Process Variation Detection and Self-Calibration Method for High-Speed Serial Links.
Proceedings of the 2018 IEEE East-West Design & Test Symposium, 2018

High Quality Factor 5.0 Gbps CTLE Circuit for SERDES Serial Links.
Proceedings of the 2018 IEEE East-West Design & Test Symposium, 2018

Transmitter Output Impedance Calibration Method.
Proceedings of the 2018 IEEE East-West Design & Test Symposium, 2018

Low Power, Low Offset, Area Efficient Comparator Design in Nanoscale CMOS Technology.
Proceedings of the 2018 IEEE East-West Design & Test Symposium, 2018

2017
P/G pad placement optimization in USB test chips.
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

Temperature-aware interactive initial placement for integrated circuits.
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

3D integrated circuits multifactor placement.
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

2016
Line-impedance matching and signal conditioning capabilities for high-speed feed-forward voltage-mode transmit drivers.
Microelectron. J., 2016

Low power OpenRISC processor with power gating, multi-VTH and multi-voltage techniques.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

Analysis of the impact of metastability phenomenon on the latency and power consumption of synchronizer circuits.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

2015
Accurate reference current generation method and circuit in CMOS.
Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015

Low power duty cycle adjustment simple method in high speed serial links.
Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015

Clock gating and multi-VTH low power design methods based on 32/28 nm ORCA processor.
Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015

2014
Pull-up/pull-down line impedance matching methodology for high speed transmitters.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

Synopsys' Educational Generic Memory Compiler.
Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014

Resistance calibration method without external precision elements.
Proceedings of the 2014 East-West Design & Test Symposium, 2014

Modified fast PCA algorithm on GPU architecture.
Proceedings of the 2014 East-West Design & Test Symposium, 2014

Design of low-ripple multi-topology step-down switched capacitor power converter with adaptive control system.
Proceedings of the 2014 East-West Design & Test Symposium, 2014

2013
PVT variation detection and compensation methods for high-speed systems.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

High accuracy equalization method for receiver active equalizer.
Proceedings of the East-West Design & Test Symposium, 2013

Self-calibration method for capacitor mismatch elimination.
Proceedings of the East-West Design & Test Symposium, 2013

Low-voltage compatible linear voltage ramp generator for zero-crossing-based integrators.
Proceedings of the East-West Design & Test Symposium, 2013

Self compensating low noise low power PLL design.
Proceedings of the East-West Design & Test Symposium, 2013

Noise effect estimation and reduction in high-speed voltage controlled oscillators.
Proceedings of the East-West Design & Test Symposium, 2013

2012
Investigating the effects of Inverted Temperature Dependence (ITD) on clock distribution networks.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Digital circuits verification with consideration of destabilizing factors.
Proceedings of the 6th IEEE International Design and Test Workshop, 2011

Programmable current biasing for low noise voltage controlled oscillators.
Proceedings of the 9th East-West Design & Test Symposium, 2011

2010
5V tolerant power clamps for mixed-voltage IC's in 65nm 2.5V salicided CMOS technology.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

A process variation detection method.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

Stable current and voltage generation under process variation.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

Schematic protection method from influence of total ionization dose effects on threshold voltage of MOS transistors.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

2009
Full-custom design project for digital VLSI and IC design courses using synopsys generic 90nm CMOS library.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2009

Synopsys' open educational design kit: Capabilities, deployment and future.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2009

2008
Digital lock detector for PLL.
Proceedings of the 2008 East-West Design & Test Symposium, 2008


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