Carol de Benito

Orcid: 0000-0001-9021-3381

According to our database1, Carol de Benito authored at least 22 papers between 1995 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
A Behavioural Compact Model for Programmable Neuromorphic ReRAM.
Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023

Implementation of a Physically Unclonable Function using LEDs and LDRs.
Proceedings of the 12th International Conference on Modern Circuits and Systems Technologies, 2023

2022
Empirical Modelling of ReRAM Measured Characteristics Using Charge and Flux.
Proceedings of the 11th International Conference on Modern Circuits and Systems Technologies, 2022

2021
A New Temperature-Based Model for the Reset Transition on ReRAM Memristive Devices.
Proceedings of the 10th International Conference on Modern Circuits and Systems Technologies, 2021

A Stochastic Switched Capacitor Memristor Emulator.
Proceedings of the 10th International Conference on Modern Circuits and Systems Technologies, 2021

2020
Stochastic-based Neural Network hardware acceleration for an efficient ligand-based virtual screening.
CoRR, 2020

2019
Self-learning perceptron using a digital memristor emulator.
Proceedings of the 8th International Conference on Modern Circuits and Systems Technologies, 2019

A Non-Quasi Static Model for Reset Voltage Variation in Memristive Devices.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

2018
A Simple Piecewise Model of Reset/Set Transitions in Bipolar ReRAM Memristive Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Exploring resistive switching-based memristors in the charge-flux domain: A modeling approach.
Int. J. Circuit Theory Appl., 2018

Effective accuracy estimation and representation error reduction for stochastic logic operations.
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

Emulating memristors in a digital environment using stochastic logic.
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

Design and implementation of passive memristor emulators using a charge-flux approach.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Purely Digital Memristor Emulator based on a Flux-Charge Model.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
An analytical delay model for ReRAM memory cells.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Cantilever NEMS relay-based SRAM devices for enhanced reliability.
Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017

2007
Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Impact of Thermal Gradients on Clock Skew and Testing.
IEEE Des. Test Comput., 2006

Leakage Power Characterization Considering Process Variations.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

2005
A compact gate-level energy and delay model of dynamic CMOS gates.
IEEE Trans. Circuits Syst. II Express Briefs, 2005

1996
A detailed analysis and electrical modeling of gate oxide shorts in MOS transistors.
J. Electron. Test., 1996

1995
A Detailed Analysis of GOS Defects in MOS Transistors: Testing Implications at Circuit Level.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995


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