Vicente Lorente

According to our database, Vicente Lorente authored at least 7 papers between 2009 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

Fast-track cache: a huge racetrack memory L1 data cache.

Hugo Tárrega, Alejandro Valero, Vicente Lorente, Salvador Petit, Julio Sahuquillo

Proceedings of the ICS '22: 2022 International Conference on Supercomputing, Virtual Event, June 28, 2022

2014

Analyzing the Optimal Voltage/Frequency Pair in Fault-Tolerant Caches.

Vicente Lorente, Alejandro Valero, Salvador Petit, Pierfrancesco Foglia, Julio Sahuquillo

Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014

2013

Enhancing Performance and Energy Consumption of HER Caches by Adding Associativity.

Vicente Lorente, Alejandro Valero, Ramon Canal

Proceedings of the Euro-Par 2013: Parallel Processing Workshops, 2013

Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes.

Vicente Lorente, Alejandro Valero, Julio Sahuquillo, Salvador Petit, Ramon Canal, Pedro López, José Duato

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Impact on Performance and Energy of the Retention Time and Processor Frequency in L1 Macrocell-Based Data Caches.

Alejandro Valero, Julio Sahuquillo, Vicente Lorente, Salvador Petit, Pedro López, José Duato

IEEE Trans. Very Large Scale Integr. Syst., 2012

Effects of Process Variation on the Access Time in SRAM Cells.

Vicente Lorente, Julio Sahuquillo

Proceedings of the Euro-Par 2012: Parallel Processing Workshops, 2012

2009

An hybrid eDRAM/SRAM macrocell to implement first-level data caches.

Alejandro Valero, Julio Sahuquillo, Salvador Petit, Vicente Lorente, Ramon Canal, Pedro López, José Duato

Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009