Vicente Lorente

According to our database1, Vicente Lorente authored at least 6 papers between 2009 and 2014.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2014
Analyzing the Optimal Voltage/Frequency Pair in Fault-Tolerant Caches.
Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014

2013
Enhancing Performance and Energy Consumption of HER Caches by Adding Associativity.
Proceedings of the Euro-Par 2013: Parallel Processing Workshops, 2013

Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Impact on Performance and Energy of the Retention Time and Processor Frequency in L1 Macrocell-Based Data Caches.
IEEE Trans. VLSI Syst., 2012

Effects of Process Variation on the Access Time in SRAM Cells.
Proceedings of the Euro-Par 2012: Parallel Processing Workshops, 2012

2009
An hybrid eDRAM/SRAM macrocell to implement first-level data caches.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009


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