Alejandro Valero

Orcid: 0000-0002-0824-5833

Affiliations:

University of Zaragoza, Spain

According to our database¹, Alejandro Valero authored at least 28 papers between 2009 and 2023.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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In proceedings

Article

PhD thesis

Dataset

Other

Bibliography

2023

On Fault-Tolerant Microarchitectural Techniques for Voltage Underscaling in On-Chip Memories of CNN Accelerators.

[BibT_eX]

[DOI]

Yamilka Toca-Díaz

Nicolás Landeros Muñoz

Ruben Gran Tejero

Alejandro Valero

Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

2022

Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators.

[BibT_eX]

[DOI]

Nicolás Landeros Muñoz

Alejandro Valero

Ruben Gran Tejero

Davide Zoni

J. Syst. Archit., 2022

Fast-track cache: a huge racetrack memory L1 data cache.

[BibT_eX]

[DOI]

Proceedings of the ICS '22: 2022 International Conference on Supercomputing, Virtual Event, June 28, 2022

peRISCVcope: A Tiny Teaching-Oriented RISC-V Interpreter.

[BibT_eX]

[DOI]

Darío Suárez Gracia

Alejandro Valero

Ruben Gran Tejero

María Villarroya-Gaudó

Víctor Viñals

Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022

2021

A learning experience toward the understanding of abstraction-level interactions in parallel applications.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2021

RRCD: Redirección de Registros Basada en Compresión de Datos para Tolerar FallosPermanentes en una GPU.

[BibT_eX]

[DOI]

CoRR, 2021

2020

DC-Patch: A Microarchitectural Fault Patching Technique for GPU Register Files.

[BibT_eX]

[DOI]

Alejandro Valero

Darío Suárez Gracia

Ruben Gran Tejero

IEEE Access, 2020

2019

An Aging-Aware GPU Register File Design Based on Data Redundancy.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2019

Efficient Management of Cache Accesses to Boost GPGPU Memory Subsystem Performance.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2019

Exposing Abstraction-Level Interactions with a Parallel Ray Tracer.

[BibT_eX]

[DOI]

Agustín Navarro-Torres

María Villarroya-Gaudó

Jesús Alastruey-Benedé

Proceedings of the Workshop on Computer Architecture Education, 2019

2018

Improving GPU Cache Hierarchy Performance with a Fetch and Replacement Cache.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2018: Parallel Processing, 2018

2017

On Microarchitectural Mechanisms for Cache Wearout Reduction.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Exploiting Data Compression to Mitigate Aging in GPU Register Files.

[BibT_eX]

[DOI]

Proceedings of the 29th International Symposium on Computer Architecture and High Performance Computing, 2017

2016

Enhancing the L1 Data Cache Design to Mitigate HCI.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2016

2015

Design of Hybrid Second-Level Caches.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2015

A reuse-based refresh policy for energy-aware eDRAM caches.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2015

2014

Analyzing the Optimal Voltage/Frequency Pair in Fault-Tolerant Caches.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014

2013

Hybrid caches: design and data management.

[BibT_eX]

[DOI]

Alejandro Valero

PhD thesis, 2013

Exploiting reuse information to reduce refresh energy in on-chip eDRAM caches.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Supercomputing, 2013

Enhancing Performance and Energy Consumption of HER Caches by Adding Associativity.

[BibT_eX]

[DOI]

Vicente Lorente

Alejandro Valero

Ramon Canal

Proceedings of the Euro-Par 2013: Parallel Processing Workshops, 2013

Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Impact on Performance and Energy of the Retention Time and Processor Frequency in L1 Macrocell-Based Data Caches.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

Design, Performance, and Energy Consumption of eDRAM/SRAM Macrocells for L1 Data Caches.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2012

Combining recency of information with selective random and a victim cache in last-level caches.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2012

Analyzing the optimal ratio of SRAM banks in hybrid caches.

[BibT_eX]

[DOI]

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

2011

MRU-Tour-based Replacement Algorithms for Last-Level Caches.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Symposium on Computer Architecture and High Performance Computing, 2011

Improving Last-Level Cache Performance by Exploiting the Concept of MRU-Tour.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2009

An hybrid eDRAM/SRAM macrocell to implement first-level data caches.

[BibT_eX]

[DOI]

Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

Alejandro Valero

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