According to our database1, Alejandro Valero authored at least 21 papers between 2009 and 2019.
Legend:Book In proceedings Article PhD thesis Other
An Aging-Aware GPU Register File Design Based on Data Redundancy.
IEEE Trans. Computers, 2019
Efficient Management of Cache Accesses to Boost GPGPU Memory Subsystem Performance.
IEEE Trans. Computers, 2019
Exposing Abstraction-Level Interactions with a Parallel Ray Tracer.
Proceedings of the Workshop on Computer Architecture Education, 2019
Improving GPU Cache Hierarchy Performance with a Fetch and Replacement Cache.
Proceedings of the Euro-Par 2018: Parallel Processing, 2018
On Microarchitectural Mechanisms for Cache Wearout Reduction.
IEEE Trans. VLSI Syst., 2017
Exploiting Data Compression to Mitigate Aging in GPU Register Files.
Proceedings of the 29th International Symposium on Computer Architecture and High Performance Computing, 2017
Enhancing the L1 Data Cache Design to Mitigate HCI.
Computer Architecture Letters, 2016
Design of Hybrid Second-Level Caches.
IEEE Trans. Computers, 2015
A reuse-based refresh policy for energy-aware eDRAM caches.
Microprocess. Microsystems, 2015
Analyzing the Optimal Voltage/Frequency Pair in Fault-Tolerant Caches.
Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014
Hybrid caches: design and data management.
PhD thesis, 2013
Exploiting reuse information to reduce refresh energy in on-chip eDRAM caches.
Proceedings of the International Conference on Supercomputing, 2013
Enhancing Performance and Energy Consumption of HER Caches by Adding Associativity.
Proceedings of the Euro-Par 2013: Parallel Processing Workshops, 2013
Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes.
Proceedings of the Design, Automation and Test in Europe, 2013
Impact on Performance and Energy of the Retention Time and Processor Frequency in L1 Macrocell-Based Data Caches.
IEEE Trans. VLSI Syst., 2012
Design, Performance, and Energy Consumption of eDRAM/SRAM Macrocells for L1 Data Caches.
IEEE Trans. Computers, 2012
Combining recency of information with selective random and a victim cache in last-level caches.
Analyzing the optimal ratio of SRAM banks in hybrid caches.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
MRU-Tour-based Replacement Algorithms for Last-Level Caches.
Proceedings of the 23rd International Symposium on Computer Architecture and High Performance Computing, 2011
Improving Last-Level Cache Performance by Exploiting the Concept of MRU-Tour.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011
An hybrid eDRAM/SRAM macrocell to implement first-level data caches.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009