Salvador Petit
Orcid: 0000-0003-2426-4134Affiliations:
- Polytechnic University of Valencia, Spain
According to our database1,
Salvador Petit
authored at least 107 papers
between 2000 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
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Online presence:
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on orcid.org
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on disca.upv.es
On csauthors.net:
Bibliography
2023
J. Big Data, 2023
Cloud White: Detecting and Estimating QoS Degradation of Latency-Critical Workloads in the Public Cloud.
Future Gener. Comput. Syst., 2023
SYNPA: SMT Performance Analysis and Allocation of Threads to Cores in ARM Processors.
CoRR, 2023
Proceedings of the 31st Euromicro International Conference on Parallel, 2023
Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques, 2023
2022
IEEE Trans. Computers, 2022
VMT: Virtualized Multi-Threading for Accelerating Graph Workloads on Commodity Processors.
IEEE Trans. Computers, 2022
Effect of Hyper-Threading in Latency-Critical Multithreaded Cloud Applications and Utilization Analysis of the Major System Resources.
Future Gener. Comput. Syst., 2022
Proceedings of the 30th Euromicro International Conference on Parallel, 2022
Proceedings of the ICS '22: 2022 International Conference on Supercomputing, Virtual Event, June 28, 2022
Proceedings of the 51st International Conference on Parallel Processing, 2022
2021
IEEE Access, 2021
2020
Phase-Aware Cache Partitioning to Target Both Turnaround Time and System Performance.
IEEE Trans. Parallel Distributed Syst., 2020
IEEE Trans. Parallel Distributed Syst., 2020
IEEE Trans. Parallel Distributed Syst., 2020
An efficient cache flat storage organization for multithreaded workloads for low power processors.
Future Gener. Comput. Syst., 2020
CoRR, 2020
Impact of the Array Shape and Memory Bandwidth on the Execution Time of CNN Systolic Arrays.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020
2019
IEEE Trans. Parallel Distributed Syst., 2019
IEEE Trans. Computers, 2019
IEEE Trans. Computers, 2019
Concurr. Comput. Pract. Exp., 2019
2018
Designing lab sessions focusing on real processors for computer architecture courses: A practical perspective.
J. Parallel Distributed Comput., 2018
Future Gener. Comput. Syst., 2018
Proceedings of the 2018 International Conference on High Performance Computing & Simulation, 2018
Proceedings of the 2018 International Conference on High Performance Computing & Simulation, 2018
Improving System Turnaround Time with Intel CAT by Identifying LLC Critical Applications.
Proceedings of the Euro-Par 2018: Parallel Processing, 2018
Proceedings of the Euro-Par 2018: Parallel Processing, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
A Hardware Approach to Fairly Balance the Inter-Thread Interference in Shared Caches.
IEEE Trans. Parallel Distributed Syst., 2017
IEEE Trans. Parallel Distributed Syst., 2017
Perf&Fair: A Progress-Aware Scheduler to Enhance Performance and Fairness in SMT Multicores.
IEEE Trans. Computers, 2017
A research-oriented course on Advanced Multicore Architecture: Contents and active learning methodologies.
J. Parallel Distributed Comput., 2017
Proceedings of the 29th International Symposium on Computer Architecture and High Performance Computing, 2017
Proceedings of the 2017 International Conference on High Performance Computing & Simulation, 2017
Application Clustering Policies to Address System Fairness with Intel's Cache Allocation Technology.
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017
2016
A dynamic execution time estimation model to save energy in heterogeneous multicores running periodic tasks.
Future Gener. Comput. Syst., 2016
Proceedings of the 24th Euromicro International Conference on Parallel, 2016
Proceedings of the International Conference on High Performance Computing & Simulation, 2016
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016
Student Research Poster: A Low Complexity Cache Sharing Mechanism to Address System Fairness.
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016
2015
Microprocess. Microsystems, 2015
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium, 2015
Proceedings of the 2015 International Conference on High Performance Computing & Simulation, 2015
Proceedings of the 2015 International Conference on High Performance Computing & Simulation, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Parallel Distributed Syst., 2014
Proceedings of the 2014 International Conference on Supercomputing, 2014
Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014
Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014
2013
Hardware-Based Generation of Independent Subtraces of Instructions in Clustered Processors.
IEEE Trans. Computers, 2013
Power-aware scheduling with effective task migration for real-time multicore embedded systems.
Concurr. Comput. Pract. Exp., 2013
Proceedings of the International Conference on Supercomputing, 2013
Proceedings of the International Conference on Computational Science, 2013
Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes.
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013
2012
Impact on Performance and Energy of the Retention Time and Processor Frequency in L1 Macrocell-Based Data Caches.
IEEE Trans. Very Large Scale Integr. Syst., 2012
A Sequentially Consistent Multiprocessor Architecture for Out-of-Order Retirement of Instructions.
IEEE Trans. Parallel Distributed Syst., 2012
J. Supercomput., 2012
Design, Performance, and Energy Consumption of eDRAM/SRAM Macrocells for L1 Data Caches.
IEEE Trans. Computers, 2012
Combining recency of information with selective random and a victim cache in last-level caches.
ACM Trans. Archit. Code Optim., 2012
Efficiently Handling Memory Accesses to Improve QoS in Multicore Systems under Real-Time Constraints.
Proceedings of the IEEE 24th International Symposium on Computer Architecture and High Performance Computing, 2012
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium, 2012
Page-Based Memory Allocation Policies of Local and Remote Memory in Cluster Computers.
Proceedings of the 18th IEEE International Conference on Parallel and Distributed Systems, 2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
OMHI 2012: First International Workshop on On-chip Memory Hierarchies and Interconnects: Organization, Management and Implementation.
Proceedings of the Euro-Par 2012: Parallel Processing Workshops, 2012
2011
A New Energy-Aware Dynamic Task Set Partitioning Algorithm for Soft and Hard Embedded Real-Time Systems.
Comput. J., 2011
Proceedings of the 23rd International Symposium on Computer Architecture and High Performance Computing, 2011
Proceedings of the Algorithms and Architectures for Parallel Processing, 2011
A Dynamic Power-Aware Partitioner with Task Migration for Multicore Embedded Systems.
Proceedings of the Euro-Par 2011 Parallel Processing - 17th International Conference, 2011
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011
2010
Dynamic task set partitioning based on balancing resource requirements and utilization to reduce power consumption.
Proceedings of the 2010 ACM Symposium on Applied Computing (SAC), 2010
Balancing Task Resource Requirements in Embedded Multithreaded Multicore Processors to Reduce Power Consumption.
Proceedings of the 18th Euromicro Conference on Parallel, 2010
Proceedings of the 28th International Conference on Computer Design, 2010
Extending a Multicore Multithread Simulator to Model Power-Aware Hard Real-Time Systems.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2010
Proceedings of the 12th IEEE International Conference on High Performance Computing and Communications, 2010
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010
2009
IEEE Trans. Computers, 2009
Intell. Autom. Soft Comput., 2009
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009
Dynamic task set partitioning based on balancing memory requirements to reduce power consumption.
Proceedings of the 23rd international conference on Supercomputing, 2009
Proceedings of the 27th International Conference on Computer Design, 2009
Proceedings of the Euro-Par 2009 Parallel Processing, 2009
An Efficient Low-Complexity Alternative to the ROB for Out-of-Order Retirement of Instructions.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
2008
The impact of out-of-order commit in coarse-grain, fine-grain and simultaneous multithreaded architectures.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008
A simple power-aware scheduling for multicore systems when running real-time applications.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008
Proceedings of the Euro-Par 2008, 2008
2007
Spim-Cache: A Pedagogical Tool for Teaching Cache Memories Through Code-Based Exercises.
IEEE Trans. Educ., 2007
Proceedings of the 19th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), 2007
Proceedings of the 2007 International Conference on Intelligent Pervasive Computing, 2007
VB-MT: Design Issues and Performance of the Validation Buffer Microarchitecture for Multithreaded Processors.
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007
2006
J. Supercomput., 2006
RACFP: a training tool to work with floating-point representation, algorithms, and circuits in undergraduate courses.
IEEE Trans. Educ., 2006
An execution-driven simulation tool for teaching cache memories in introductory computer organization courses.
Proceedings of the 2006 Workshop on Computer Architecture Education, 2006
Proceedings of the 18th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2006), 2006
2005
Exploring the performance of split data cache schemes on superscalar processors and symmetric multiprocessors.
J. Syst. Archit., 2005
Proceedings of the 13th Euromicro Workshop on Parallel, 2005
Proceedings of the Second Conference on Computing Frontiers, 2005
2004
Proceedings of the 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2004), 2004
2002
Characterizing Parallel Workloads to Reduce Multiple Writer Overhead in Shared Virtual Memory Systems.
Proceedings of the 10th Euromicro Workshop on Parallel, 2002
2001
Proceedings of the 2001 IEEE International Symposium on Performance Analysis of Systems and Software, 2001
2000
SIGARCH Comput. Archit. News, 2000