Alexandre Schmid
Orcid: 0000-0002-6730-0193
According to our database1,
Alexandre Schmid
authored at least 112 papers
between 1999 and 2024.
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Bibliography
2024
Dynamic Probabilistic Pruning: A General Framework for Hardware-Constrained Pruning at Different Granularities.
IEEE Trans. Neural Networks Learn. Syst., January, 2024
A Two-Wired High Input Impedance and High CMRR Active Electrode Insensitive to Component Mismatch.
IEEE Trans. Instrum. Meas., 2024
2023
IEEE Trans. Circuits Syst. II Express Briefs, May, 2023
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023
Digital One-Shot Charge-balancing Method for Implantable Current-Mode Electrical Stimulation.
Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023
Design of a Dual-Band Wireless Power and Data Transfer Coil for Multisite Biomedical Implants.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2023
Programmable Seizure Detector Using a 32-bit RISC Processor for Implantable Medical Devices.
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023
A 13.56 MHz Active Rectifier with Digitally-Assisted and Delay Compensated Comparators for Biomedical Implantable Devices.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023
A Wireless Power and Bi-Directional Data Transfer System Using A Single Inductive Link for Biomedical Implants.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023
2022
Epileptic Seizure Detection With Patient-Specific Feature and Channel Selection for Low-power Applications.
IEEE Trans. Biomed. Circuits Syst., 2022
Electrical Model of a Wireless mW-Power and Mbps-Data Transfer System Over a Single Pair of Coils.
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022
Simultaneous Wireless Power and Data Transmission Through a Single Inductive Link For Multiple Implantable Medical Devices.
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022
Structured and tiled-based pruning of Deep Learning models targeting FPGA implementations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2022
2021
Walsh-Hadamard-Based Orthogonal Sampling Technique for Parallel Neural Recording Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Two-stage Hardware-Friendly Epileptic Seizure Detection Method with a Dynamic Feature Selection.
Proceedings of the 43rd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2021
Hardware-oriented pruning and quantization of Deep Learning models to detect life-threatening arrhythmias.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, BioCAS 2021, 2021
2020
A Review of Microelectronic Systems and Circuit Techniques for Electrical Neural Recording Aimed at Closed-Loop Epilepsy Control.
Sensors, 2020
2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
2018
A Sub-µW/Channel, 16-Channel Seizure Detection and Signal Acquisition SoC Based on Multichannel Compressive Sensing.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
Protocomputing Architecture over a Digital Medium Aiming at Real-Time Video Processing.
Complex., 2018
Implantable IoT System for Closed-Loop Epilepsy Control based on Electrical Neuromodulation.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
A Fully Fail-Safe Capacitive-Based Charge Metering Method for Active Charge Balancing in Deep Brain Stimulation.
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018
Current Overshoots and Undershoots in Electrical Stimulation: A Circuit-level Perspective of the Origin and Solutions.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
All Wireless, 16-Channel Epilepsy Control System with Sub-µW/Channel and Closed-Loop Stimulation Using a Switched-Capacitor-Based Active Charge Balancing Method.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
A 4-channel 5.04 μW 0.325 mm<sup>2</sup> Orthogonal Sampling-Based Parallel Neural Recording System.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
Error Tolerance Analysis of Deep Learning Hardware Using a Restricted Boltzmann Machine Toward Low-Power Memory Implementation.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Compact, Energy-Efficient High-Frequency Switched Capacitor Neural Stimulator With Active Charge Balancing.
IEEE Trans. Biomed. Circuits Syst., 2017
Live demonstration: Feature extraction system using restricted Boltzmann machines on FPGA.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017
A compact size charge-mode stimulator using a low-power active charge balancing method for deep brain stimulation (DBS).
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017
2016
Motion Vector Estimation of Textureless Objects Exploiting Reaction-Diffusion Cellular Automata.
Int. J. Unconv. Comput., 2016
A 16-channel 1.1mm<sup>2</sup> implantable seizure control SoC with sub-μW/channel consumption and closed-loop stimulation in 0.18µm CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
A time-based, digitally intensive circuit and system architecture for wireless neural recording with high dynamic range.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016
Memory-error tolerance of scalable and highly parallel architecture for restricted Boltzmann machines in Deep Belief Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Bit-flipping LDPC under noise conditions and its application to physically unclonable functions.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016
2015
A Real-Time Multiaperture Omnidirectional Visual Sensor Based on an Interconnected Network of Smart Cameras.
IEEE Trans. Circuits Syst. Video Technol., 2015
Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
IEEE Trans. Circuits Syst. II Express Briefs, 2015
A comparative experimental investigation on responsivity and response speed of photo-diode and photo-BJT structures integrated in a low-cost standard CMOS process.
Microelectron. J., 2015
A sub-mW pulse-based 5-bit flash ADC with a time-domain fully-digital reference ladder.
Microelectron. J., 2015
A subthreshold current-sensing ΣΔ modulator for low-voltage and low-power sensor interfaces.
Int. J. Circuit Theory Appl., 2015
Int. J. Circuit Theory Appl., 2015
Trinocular adaptive window size disparity estimation algorithm and its real-time hardware.
Proceedings of the VLSI Design, Automation and Test, 2015
An implantable high-voltage cortical stimulator for post-stroke rehabilitation enhancement with high-current driving capacity.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Live demonstration: Real-time free viewpoint synthesis using three-camera disparity estimation hardware.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
J. Signal Process. Syst., 2014
Compact Low-Power Cortical Recording Architecture for Compressive Multichannel Data Acquisition.
IEEE Trans. Biomed. Circuits Syst., 2014
Dynamically adaptive real-time disparity estimation hardware using iterative refinement.
Integr., 2014
Proceedings of the VLSI-SoC: Internet of Things Foundations, 2014
A 5.43-μW 0.8-V subthreshold current-sensing ΣΔ modulator for low-noise sensor interfaces.
Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014
A retina-inspired robust on-focal-plane multi-band edge-detection scheme for CMOS image sensors.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Tunnel FET-based ultra-low power, low-noise amplifier design for bio-signal acquisition.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014
A novel compressive sensing architecture for high-density biological signal recording.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014
2013
J. Signal Process. Syst., 2013
Hemispherical Multiple Camera System for High Resolution Omni-Directional Light Field Imaging.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2013
Proceedings of the VLSI-SoC: At the Crossroads of Emerging Trends, 2013
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
A low-power area-efficient compressive sensing approach for multi-channel neural recording.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the IEEE International Conference on Acoustics, 2013
Proceedings of the IEEE International Conference on Acoustics, 2013
High frame-rate low-power compressive sampling CMOS image sensor architecture: [extended abstract].
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
A hardware-oriented dynamically adaptive disparity estimation algorithm and its real-time hardware.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
A spherical multi-camera system with real-time omnidirectional video acquisition capability.
IEEE Trans. Consumer Electron., 2012
Proceedings of the Symposium on VLSI Circuits, 2012
Real-Time FPGA Implementation of Linear Blending Vision Reconstruction Algorithm Using a Spherical Light Field Camera.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012
Design techniques and analysis of high-resolution neural recording systems targeting epilepsy focus localization.
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Design and Implementation of Multi-camera Systems Distributed over a Spherical Geometry.
Proceedings of the Diagrammatic Representation and Inference, 2012
2011
Energy Efficient Low-Noise Neural Recording Amplifier With Enhanced Noise Efficiency Factor.
IEEE Trans. Biomed. Circuits Syst., 2011
IEICE Electron. Express, 2011
2010
Output probability density functions of logic circuits: Modeling and fault-tolerance evaluation.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Selective redundancy-based design techniques for the minimization of local delay variations.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
A (256×256) pixel 76.7mW CMOS imager/ compressor based on real-time In-pixel compressive sensing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
Electrical modeling of the cell-electrode interface for recording neural activity from high-density microelectrode arrays.
Neurocomputing, 2009
Int. J. Nanotechnol. Mol. Comput., 2009
Int. J. Nanotechnol. Mol. Comput., 2009
Proceedings of the Nano-Net - 4th International ICST Conference, 2009
A pulse-density modulation circuit exhibiting noise shaping with single-electron neurons.
Proceedings of the International Joint Conference on Neural Networks, 2009
Proceedings of the IEEE International Conference on Acoustics, 2009
Proceedings of the 35th European Solid-State Circuits Conference, 2009
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009
Optimization of Nanoelectronic Systems Reliability Under Massive Defect Density Using Distributed R-fold Modular Redundancy (DRMR).
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
2008
CMOS realization of two-dimensional mixed analog-digital Hamming distance discriminator circuits for real-time imaging applications.
Microelectron. J., 2008
Proceedings of the Design, Automation and Test in Europe, 2008
2007
A 90nm CMOS cryptographic core with improved fault-tolerance in presence of massive defect density.
Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007
Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
2006
Fault-Tolerance of Robust Feed-Forward Architecture Using Single-Ended and Differential Deep-Submicron Circuits Under Massive Defect Density.
Proceedings of the International Joint Conference on Neural Networks, 2006
2005
On the fault tolerance of a clustered single-electron neural network for differential enhancement.
IEICE Electron. Express, 2005
A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on a-priori Functional Fault- Tolerance Analysis.
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005
Single-electron circuit for inhibitory spiking neural network with fault-tolerant architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005
2004
Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors.
IEEE Trans. Very Large Scale Integr. Syst., 2004
Robust and fault-tolerant circuit design for nanometer-scale devices and single-electron transistors.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Mixed analog-digital image processing circuit based on Hamming artificial neural network architecture.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
A Highly Fault Tolerant PLA Architecture for Failure-Prone Nanometer CMOS and Novel Quantum Device Technologies.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004
2003
VLSI Realization of a Two-Dimensional Hamming Distance Comparator ANN for Image Processing Applications.
Proceedings of the 11th European Symposium on Artificial Neural Networks, 2003
1999
A novel analog-digital flash converter architecture based on capacitive threshold gates.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the International Joint Conference Neural Networks, 1999
Proceedings of the 5th European Control Conference, 1999