Vincent von Kaenel

According to our database, Vincent von Kaenel authored at least 8 papers between 1990 and 2007.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2007

A 25W SoC with Dual 2GHz Power Cores and Integrated Memory and I/O Subsystems.

Zongjian Chen, Priya Ananthanarayanan, Sukalp Biswas, Brian Campbell, Hao Chen, Shaishav Desai, Dominic Go, Rajat Goel, Vincent von Kaenel, Jason Kassoff, Fabian Klass, Weichun Ku, Tony Li, Jonathon Lin, Khurram Malik, Anup Mehta, Daniel Murray, Eric Shiu, Chris Shuler, Sribalan Santhanam, Greg Scott, Junji Sugisawa, Toshinari Takayanagi, Honkai John Tarn, Pradeep Trivedi, James Wang, Ricky Wen, John Yong

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Dual True Random Number Generators for Cryptographic Applications Embedded on a 200 Million Device Dual CPU SoC.

Vincent von Kaenel, Toshinari Takayanagi

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

Power-Efficient Dual-Supply 64kB L1 Caches in a 65nm CMOS Technology.

Brian Campbell, James Burnette, Naveen Javarappa, Vincent von Kaenel

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2003

A 2× load/store pipe for a low-power 1-GHz embedded processor.

Zongjian Chen, Daniel Murray, Steve Nishimoto, Mark H. Pearce, Max Oyker, Daniel Rodriguez, Robert Rogenmoser, Dongwook (Drew) Suh, Erik Supnet, Vincent von Kaenel, George Yiu

IEEE J. Solid State Circuits, 2003

1997

A 2.1-MHz crystal oscillator time base with a current consumption under 500 nA.

Daniel Aebischer, Henri J. Oguey, Vincent von Kaenel

IEEE J. Solid State Circuits, 1997

1996

A 320 MHz, 1.5 mW@1.35 V CMOS PLL for microprocessor clock generation.

Vincent von Kaenel, Daniel Aebischer, Christian Piguet, Evert Dijkstra

IEEE J. Solid State Circuits, 1996

1995

Logic design for low-voltage/low-power CMOS circuits.

Christian Piguet, Jean-Marc Masgonty, Vincent von Kaenel, Thierry Schneider

Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

1990

A voltage reduction technique for battery-operated systems.

Vincent von Kaenel, Peter Macken, Marc G. R. Degrauwe

IEEE J. Solid State Circuits, October, 1990