Vinesh Srinivasan

According to our database1, Vinesh Srinivasan authored at least 6 papers between 2012 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
Slipstream Processors Revisited: Exploiting Branch Sets.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

2017
H3 (Heterogeneity in 3D): A Logic-on-Logic 3D-Stacked Heterogeneous Multi-Core Processor.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

2015
Under 100-cycle thread migration latency in a single-ISA heterogeneous multi-core processor.
Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

2013
Performance and energy efficient cache system design: Simultaneous execution of multiple applications on heterogeneous cores.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

2012



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