Vinod Pangracious

According to our database1, Vinod Pangracious authored at least 25 papers between 2009 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
3D-cool: Design and development of adaptive thermal-aware three-dimensional NoC-based multiprocessor chip.
Proceedings of the 2018 IEEE Symposium in Low-Power and High-Speed Chips, 2018

2017
A review of feature extraction for EEG epileptic seizure detection and classification.
Proceedings of the 40th International Conference on Telecommunications and Signal Processing, 2017

Thermal Management in 3D Homogeneous NoC Systems Using Optimized Placement of Liquid Microchannels.
Proceedings of the 11th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2017

2016
Novel Three-Dimensional Embedded FPGA Technology and Achitecture.
SIGARCH Computer Architecture News, 2016

Improvement of cluster-based Mesh FPGA architecture using novel hierarchical interconnect topology and long routing wires.
Microprocess. Microsystems, 2016

Exploration of Mesh-Based FPGA Architecture: Comparison of 2D and 3D Technologies in Terms of Power, Area and Performance.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

2015
Three-Dimensional Design Methodologies for Tree-based FPGA Architecture
Lecture Notes in Electrical Engineering 350, Springer, ISBN: 978-3-319-19174-4, 2015

Design and Optimization of a Horizontally Partitioned, High-Speed, 3D Tree-Based FPGA.
IEEE Micro, 2015

Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014
Architecture level optimization of 3-dimensional tree-based FPGA.
Microelectron. J., 2014

On wiring delays reduction of tree-based FPGA using 3-D fabric.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

Exploration and optimization of heterogeneous interconnect fabric of 3D tree-based FPGA.
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

Three-dimensional Mesh of Clusters: An alternative unified high performance interconnect architecture for 3D-FPGA implementation.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

2013
Exploration environment for 3D heterogeneous tree-based FPGA architectures (3D HT-FPGA).
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Designing 3D tree-based FPGA: Interconnect optimization and thermal analysis.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

TSV count minimization and thermal analysis for 3D Tree-based FPGA.
Proceedings of 2013 International Conference on IC Design & Technology, 2013

Physical design exploration of 3D tree-based FPGA architecture.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Design and optimization of heterogeneous tree-based FPGA using 3D technology.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Architecture level TSV count minimization methodology for 3D tree-based FPGA.
Proceedings of the 2013 IEEE Symposium on Low-Power and High-Speed Chips, 2013

Performance Analysis and Optimization of High Density Tree-Based 3D Multilevel FPGA.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

Designing a 3D tree-based FPGA: Optimization of butterfly programmable interconnect topology using 3D technology.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012
Thermal analysis & optimization of a 3 dimensional heterogeneous structure
CoRR, 2012

A Novel Methodology for Thermal Aware Silicon Area Estimation for 2D & 3D MPSoCs
CoRR, 2012

2011
A Novel Methodology for Thermal Analysis & 3-Dimensional Memory Integration
CoRR, 2011

2009
Through Silicon Via-Based Grid for Thermal Control in 3D Chips.
Proceedings of the Nano-Net - 4th International ICST Conference, 2009


  Loading...