Angeliki Kritikakou
Orcid: 0000-0002-9293-469X
According to our database1,
Angeliki Kritikakou
authored at least 69 papers
between 2010 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2024
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024
2023
ACM Trans. Sens. Networks, November, 2023
ACM Trans. Design Autom. Electr. Syst., September, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023
Near-optimal energy-efficient partial-duplication task mapping of real-time parallel applications.
J. Syst. Archit., 2023
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023
harDNNing: a machine-learning-based framework for fault tolerance assessment and protection of DNNs.
Proceedings of the IEEE European Test Symposium, 2023
Impact of Transient Faults on Timing Behavior and Mitigation with Near-Zero WCET Overhead.
Proceedings of the 35th Euromicro Conference on Real-Time Systems, 2023
Design with low complexity fine-grained Dual Core Lock-Step (DCLS) RISC-V processors.
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
Microprocess. Microsystems, September, 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Int. J. Parallel Program., 2022
Front Matter - ECRTS 2022 Artifacts, Table of Contents, Preface, Artifact Evaluation Committee.
Dagstuhl Artifacts Ser., 2022
Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022
Evaluating the Impact of Mixed-Precision on Fault Propagation for Deep Neural Networks on GPUs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022
Energy Efficient, Real-time and Reliable Task Deployment on NoC-based Multicores with DVFS.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Real-time and reliable design for safety-critical embedded systems. (Conception temps réel et fiable pour les systèmes embarqués critiques en matière de sécurité).
, 2022
2021
Softw. Pract. Exp., 2021
IEEE Internet Things J., 2021
Front Matter - ECRTS 2021 Artifacts, Table of Contents, Artifact Evaluation Committee.
Dagstuhl Artifacts Ser., 2021
ACM Comput. Surv., 2021
Fault-Tolerant Mapping of Real-Time Parallel Applications under multiple DVFS schemes.
Proceedings of the 27th IEEE Real-Time and Embedded Technology and Applications Symposium, 2021
A Region-Based Bit-Shuffling Approach Trading Hardware Cost and Fault Mitigation Efficiency.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
2020
Energy-Aware Partial-Duplication Task Mapping Under Real-Time and Reliability Constraints.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2020
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Multiple Permanent Faults Mitigation Through Bit-Shuffling for Network-an-Chip Architecture.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020
Progress-aware Dynamic Slack Exploitation in Mixed-critical Systems: Work-in-Progress.
Proceedings of the 20th International Conference on Embedded Software, 2020
Proceedings of the 32nd Euromicro Conference on Real-Time Systems, 2020
2019
Event-Driven Joint Mobile Actuators Scheduling and Control in Cyber-Physical Systems.
IEEE Trans. Ind. Informatics, 2019
Peer-to-Peer Netw. Appl., 2019
Energy-Aware Multiple Mobile Chargers Coordination for Wireless Rechargeable Sensor Networks.
IEEE Internet Things J., 2019
Timely Fine-Grained Interference-Sensitive Run-Time Adaptation of Time-Triggered Schedules.
Proceedings of the IEEE Real-Time Systems Symposium, 2019
Fine-Grained Hardware Mitigation for Multiple Long-Duration Transients on VLIW Function Units.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the 2019 Conference on Design and Architectures for Signal and Image Processing, 2019
2018
DYNASCORE: DYNAmic Software COntroller to Increase REsource Utilization in Mixed-Critical Systems.
ACM Trans. Design Autom. Electr. Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Distributed Node Coordination for Real-Time Energy-Constrained Control in Wireless Sensor and Actuator Networks.
IEEE Internet Things J., 2018
Controllable QoS for Imprecise Computation Tasks on DVFS Multicores With Time and Energy Constraints.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
Collaborative State Estimation and Actuator Scheduling for Cyber-Physical Systems Under Random Multiple Events.
Proceedings of the Ad-hoc, Mobile, and Wireless Networks, 2018
2017
Run-time Instruction Replication for permanent and soft error mitigation in VLIW processors.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
WCET-aware parallelization of model-based applications for multi-cores: The ARGO approach.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
ACM Trans. Design Autom. Electr. Syst., 2016
A high-performance matrix-matrix multiplication methodology for CPU and GPU architectures.
J. Supercomput., 2016
2015
A methodology for speeding up matrix vector multiplication for single/multi-core architectures.
J. Supercomput., 2015
A methodology for speeding up loop kernels by exploiting the software information and the memory architecture.
Comput. Lang. Syst. Struct., 2015
2014
A Methodology for Speeding up MVM for Regular, Toeplitz and Bisymmetric Toeplitz Matrices.
J. Signal Process. Syst., 2014
A Matrix-Matrix Multiplication methodology for single/multi-core architectures using SIMD.
J. Supercomput., 2014
A methodology for speeding up edge and line detection algorithms focusing on memory architecture utilization.
J. Supercomput., 2014
ACM Trans. Archit. Code Optim., 2014
Distributed run-time WCET controller for concurrent critical tasks in mixed-critical systems.
Proceedings of the 22nd International Conference on Real-Time Networks and Systems, 2014
Proceedings of the 26th Euromicro Conference on Real-Time Systems, 2014
2013
Near-optimal and scalable intrasignal in-place optimization for non-overlapping and irregular access schemes.
ACM Trans. Design Autom. Electr. Syst., 2013
Near-Optimal Microprocessor and Accelerators Codesign with Latency and Throughput Constraints.
ACM Trans. Archit. Code Optim., 2013
ACM Comput. Surv., 2013
2012
J. Supercomput., 2012
A template-based methodology for efficient microprocessor and FPGA accelerator co-design.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012
Proceedings of 2012 IEEE 17th International Conference on Emerging Technologies & Factory Automation, 2012
2011
A Methodology for Speeding Up Fast Fourier Transform Focusing on Memory Architecture Utilization.
IEEE Trans. Signal Process., 2011
Proceedings of the IEEE 16th Conference on Emerging Technologies & Factory Automation, 2011
2010
Ultra High Speed SHA-256 Hashing Cryptographic Module for IPSec Hardware/Software Codesign.
Proceedings of the SECRYPT 2010, 2010
Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010