Vivek Govindaraj

According to our database, Vivek Govindaraj authored at least 6 papers between 2016 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2022

A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking.

Yizhe Hu, Xi Chen, Teerachot Siriburanon, Jianglin Du, Vivek Govindaraj, Anding Zhu, Robert Bogdan Staszewski

IEEE J. Solid State Circuits, 2022

2021

A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL.

Jianglin Du, Teerachot Siriburanon, Yizhe Hu, Vivek Govindaraj, Robert Bogdan Staszewski

IEEE J. Solid State Circuits, 2021

A 24-31 GHz Reference Oversampling ADPLL Achieving FoMjitter-N of -269.3 dB.

Jianglin Du, Teerachot Siriburanon, Xi Chen, Yizhe Hu, Vivek Govindaraj, Anding Zhu, Robert Bogdan Staszewski

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

2020

17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and -250dB FoM.

Yizhe Hu, Xi Chen, Teerachot Siriburanon, Jianglin Du, Zhong Gao, Vivek Govindaraj, Anding Zhu, Robert Bogdan Staszewski

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019

DTC-Assisted All-Digital Phase-Locked Loop Exploiting Hybrid Time/Voltage Phase Digitization.

Vivek Govindaraj, Jianglin Du, Yizhe Hu, Teerachot Siriburanon, Robert Bogdan Staszewski

Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019

2016

Virtual Multi-Antenna Array for Estimating the Angle-of-Arrival of a RF Transmitter.

François Quitin, Vivek Govindaraj, Xionghu Zhong, Wee-Peng Tay

Proceedings of the IEEE 84th Vehicular Technology Conference, 2016