Jianglin Du
Orcid: 0000-0002-4533-3576
According to our database1,
Jianglin Du
authored at least 11 papers
between 2019 and 2023.
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Collaborative distances:
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Bibliography
2023
A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain-Gate-Source for Low Flicker Phase Noise and I/Q Exactness.
IEEE J. Solid State Circuits, 2023
2022
Flicker Phase-Noise Reduction Using Gate-Drain Phase Shift in Transformer-Based Oscillators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking.
IEEE J. Solid State Circuits, 2022
A Compact 0.2-0.3-V Inverse-Class-F<sub>23</sub> Oscillator for Low 1/f<sup>3</sup> Noise Over Wide Tuning Range.
IEEE J. Solid State Circuits, 2022
2021
Dickson-Charge-Pump-Based Voltage-to-Time Conversion for Time-Based ADCs in 28-nm CMOS.
IEEE Open J. Circuits Syst., 2021
IEEE J. Solid State Circuits, 2021
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
2020
17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and -250dB FoM.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
A 0.3V, 35% Tuning-Range, 60kHz 1/f<sup>3</sup>-Corner Digitally Controlled Oscillator with Vertically Integrated Switched Capacitor Banks Achieving FoMT of -199dB in 28-nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
DTC-Assisted All-Digital Phase-Locked Loop Exploiting Hybrid Time/Voltage Phase Digitization.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019