Xi Chen

Orcid: 0000-0002-2210-0075

Affiliations:
  • University College Dublin, UCD, School of Electrical and Electronic Engineering, Ireland (PhD 2022)


According to our database1, Xi Chen authored at least 6 papers between 2020 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2023
A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain-Gate-Source for Low Flicker Phase Noise and I/Q Exactness.
IEEE J. Solid State Circuits, 2023

2022
A G<sub>m</sub>-Boosting Technique for Millimeter-Wave Low-Noise Amplifiers in 28-nm Triple-Well Bulk CMOS Using Floating Resistor in Body Biasing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Flicker Phase-Noise Reduction Using Gate-Drain Phase Shift in Transformer-Based Oscillators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking.
IEEE J. Solid State Circuits, 2022

2021
A 24-31 GHz Reference Oversampling ADPLL Achieving FoMjitter-N of -269.3 dB.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

2020
17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and -250dB FoM.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020


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