Vyas Venkataraman

According to our database, Vyas Venkataraman authored at least 5 papers between 2008 and 2009.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2009

Simulation of a Heterogeneous System at Multiple Levels of Abstraction Using Rendezvous Based Modeling.

Vyas Venkataraman, Di Wang, Wei Qin, Mrinal Bose, Jayanta Bhadra

Proceedings of the 10th International Workshop on Microprocessor Test and Verification, 2009

Synthesis Oriented Scheduling of Multiparty Rendezvous in Transaction Level Models.

Vyas Venkataraman, Di Wang, Atabak Mahram, Wei Qin, Mrinal Bose, Jayanta Bhadra

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

Accelerating multi-party scheduling for transaction-level modeling.

Di Wang, Vyas Venkataraman, Zhen Wang, Wei Qin, Hangsheng Wang, Mrinal Bose, Jayanta Bhadra

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

2008

Asynchronous balanced gates tolerant to interconnect variability.

Konrad J. Kulikowski, Vyas Venkataraman, Zhen Wang, Alexander Taubin, Mark G. Karpovsky

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Power Balanced Gates Insensitive to Routing Capacitance Mismatch.

Konrad J. Kulikowski, Vyas Venkataraman, Zhen Wang, Alexander Taubin

Proceedings of the Design, Automation and Test in Europe, 2008