Alexander Taubin

According to our database1, Alexander Taubin authored at least 36 papers between 1991 and 2009.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2009
Guest Editorial: Special Section on Asynchronous Circuits and Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Elastic Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Heuristic Based throughput Analysis and Optimization of Asynchronous Pipelines.
Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009

2008
Asynchronous balanced gates tolerant to interconnect variability.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Power Balanced Gates Insensitive to Routing Capacitance Mismatch.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Robust codes and robust, fault-tolerant architectures of the Advanced Encryption Standard.
J. Syst. Archit., 2007

Design Automation of Real-Life Asynchronous Devices and Systems.
Found. Trends Electron. Des. Autom., 2007

A Highly Scalable GALS Crossbar Using Token Ring Arbitration.
IEEE Des. Test Comput., 2007

2006
Power Attacks on Secure Hardware Based on Early Propagation of Data.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

DPA on Faulty Cryptographic Hardware and Countermeasures.
Proceedings of the Fault Diagnosis and Tolerance in Cryptography, 2006

Fault Attack Resistant Cryptographic Hardware with Uniform Error Detection.
Proceedings of the Fault Diagnosis and Tolerance in Cryptography, 2006

Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2006

2005
Delay Insensitive Encoding and Power Analysis: A Balancing Act.
Proceedings of the 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 2005

An Automated Fine-Grain Pipelining Using Domino Style Asynchronous Library.
Proceedings of the Fifth International Conference on Application of Concurrency to System Design (ACSD 2005), 2005

2004
New Class of Nonlinear Systematic Error Detecting Codes.
IEEE Trans. Inf. Theory, 2004

Quasi-static Scheduling for Concurrent Architectures.
Fundam. Informaticae, 2004

Robust Protection against Fault-Injection Attacks on Smart Cards Implementing the Advanced Encryption Standard.
Proceedings of the 2004 International Conference on Dependable Systems and Networks (DSN 2004), 28 June, 2004

Differential Fault Analysis Attack Resistant Architectures for the Advanced Encryption Standard.
Proceedings of the Smart Card Research and Advanced Applications VI, 2004

2002
Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Design of Delay-Insensitive Three Dimension Pipeline Array Multiplier for Image Processing.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Checking Delay-Insensitivity: 10<sup>4</sup> Gates and Beyond.
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002

2000
Asynchronous Design Using Commercial HDL Synthesis Tools.
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000

1999
Behavioral Transformations to Increase Noise Immunity in Asynchronous Specifications.
Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999

1998
Partial-scan delay fault testing of asynchronous circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

The Use of Petri Nets for the Design and Verification of Asynchronous Circuits and Systems.
J. Circuits Syst. Comput., 1998

Analysis of Petri Nets by Ordering Relations in Reduced Unfoldings.
Formal Methods Syst. Des., 1998

Lazy transition systems: application to timing optimization of asynchronous circuits.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Identifying State Coding Conflicts in Asynchronous System Specifications Using Petri Net Unfoldings.
Proceedings of the 1st International Conference on Application of Concurrency to System Design (ACSD '98), 1998

1997
Coupling Asynchrony and Interrupts: Place Chart Nets.
Proceedings of the Application and Theory of Petri Nets 1997, 1997

1996
A Structural Approach for the Analysis of Petri Nets by Reduced Unfoldings.
Proceedings of the Application and Theory of Petri Nets 1996, 1996

1994
Specification and analysis of self-timed circuits.
J. VLSI Signal Process., 1994

Analysis and Identification of Speed-Independent Circuits on an Event Model.
Formal Methods Syst. Des., 1994

Change Diagram : A behavioural model for very speed VLSI circuit/highly parallel systems.
Proceedings of the Second Euromicro Workshop on Parallel and Distributed Processing, 1994

Verification of the speed-independent circuits by STG unfoldings.
Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1994

1992
Analysis and Identification of Self-Timed Circuits.
Proceedings of the Designing Correct Circuits, 1992

1991
Formal method for self-timed design.
Proceedings of the conference on European design automation, 1991


  Loading...