Vyas Venkataraman

According to our database1, Vyas Venkataraman authored at least 5 papers between 2008 and 2009.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2009
Simulation of a Heterogeneous System at Multiple Levels of Abstraction Using Rendezvous Based Modeling.
Proceedings of the 10th International Workshop on Microprocessor Test and Verification, 2009

Synthesis Oriented Scheduling of Multiparty Rendezvous in Transaction Level Models.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

Accelerating multi-party scheduling for transaction-level modeling.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

2008
Asynchronous balanced gates tolerant to interconnect variability.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Power Balanced Gates Insensitive to Routing Capacitance Mismatch.
Proceedings of the Design, Automation and Test in Europe, 2008


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