Wael M. Elsharkasy

According to our database1, Wael M. Elsharkasy authored at least 5 papers between 2013 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2017
Reliability Enhancement of Low-Power Sequential Circuits Using Reconfigurable Pulsed Latches.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

AS8-static random access memory (SRAM): asymmetric SRAM architecture for soft error hardening enhancement.
IET Circuits Devices Syst., 2017

Efficient pulsed-latch implementation for multiport register files: work-in-progress.
Proceedings of the 2017 International Conference on Compilers, 2017

2015
NUVA: Architectural support for runtime verification of parametric specifications over multicores.
Proceedings of the 2015 International Conference on Compilers, 2015

2013
Low overhead correction scheme for unreliable LDPC buffering.
Proceedings of the IEEE Global Conference on Signal and Information Processing, 2013


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