According to our database1, Amin Khajeh authored at least 30 papers between 2007 and 2018.
Legend:Book In proceedings Article PhD thesis Other
Enhancing Power, Performance, and Energy Efficiency in Chip Multiprocessors Exploiting Inverse Thermal Dependence.
IEEE Trans. VLSI Syst., 2018
Microarchitecture-Level SoC Design.
Proceedings of the Handbook of Hardware/Software Codesign., 2017
Reliability Enhancement of Low-Power Sequential Circuits Using Reconfigurable Pulsed Latches.
IEEE Trans. on Circuits and Systems, 2017
Efficient pulsed-latch implementation for multiport register files: work-in-progress.
Proceedings of the 2017 International Conference on Compilers, 2017
A System-Level Exploration of Power Delivery Architectures for Near-Threshold Manycores Considering Performance Constraints.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Revisiting Dynamic Thermal Management Exploiting Inverse Thermal Dependence.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
Multicopy Cache: A Highly Energy-Efficient Cache Architecture.
ACM Trans. Embedded Comput. Syst., 2014
Joint Power Management and Adaptive Modulation and Coding for Wireless Communications Systems With Unreliable Buffering Memories.
IEEE Trans. on Circuits and Systems, 2014
Equi-Noise: A Statistical Model That Combines Embedded Memory Failures and Channel Noise.
IEEE Trans. on Circuits and Systems, 2014
A survey of cross-layer power-reliability tradeoffs in multi and many core systems-on-chip.
Microprocessors and Microsystems - Embedded Hardware Design, 2013
Low overhead correction scheme for unreliable LDPC buffering.
Proceedings of the IEEE Global Conference on Signal and Information Processing, 2013
Error-aware power management for memory dominated OFDM systems.
Proceedings of the 2013 Asilomar Conference on Signals, 2013
Error-Aware Algorithm/Architecture Coexploration for Video Over Wireless Applications.
ACM Trans. Embedded Comput. Syst., 2012
Fast error aware model for arithmetic and logic circuits.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
Embedded Memories Fault-Tolerant Pre- and Post-Silicon Optimization.
IEEE Trans. VLSI Syst., 2011
A Class of Low Power Error Compensation Iterative Decoders.
Proceedings of the Global Communications Conference, 2011
Reliability-aware placement in SRAM-based FPGA for voltage scaling realization in the presence of process variations.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011
Low-Power Multimedia System Design by Aggressive Voltage Scaling.
IEEE Trans. VLSI Syst., 2010
Effect of body biasing on embedded SRAM failure.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
A Unified Hardware and Channel Noise Model for Communication Systems.
Proceedings of the Global Communications Conference, 2010
Process variation aware transcoding for low power H.264 decoding.
Proceedings of the 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia, 2010
E < MC2: less energy through multi-copy cache.
Proceedings of the 2010 International Conference on Compilers, 2010
A Low Power JPEG2000 Encoder With Iterative and Fault Tolerant Error Concealment.
IEEE Trans. VLSI Syst., 2009
TRAM: A tool for Temperature and Reliability Aware Memory Design.
Proceedings of the Design, Automation and Test in Europe, 2009
Cross-layer co-exploration of exploiting error resilience for video over wireless applications.
Proceedings of the 6th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2008
Fault Tolerant Approaches Targeting Ultra Low Power Communications System Design.
Proceedings of the 65th IEEE Vehicular Technology Conference, 2007
Cross Layer Error Exploitation for Aggressive Voltage Scaling.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Limits on voltage scaling for caches utilizing fault tolerant techniques.
Proceedings of the 25th International Conference on Computer Design, 2007
Power Management for Cognitive Radio Platforms.
Proceedings of the Global Communications Conference, 2007
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007