Smaïl Niar

According to our database1, Smaïl Niar authored at least 101 papers between 1997 and 2018.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
HAPE: A high-level area-power estimation framework for FPGA-based accelerators.
Microprocessors and Microsystems - Embedded Hardware Design, 2018

Power optimization techniques for associative processors.
Journal of Systems Architecture - Embedded Systems Design, 2018

An effective and distributed particle swarm optimization algorithm for flexible job-shop scheduling problem.
J. Intelligent Manufacturing, 2018

Efficient modelling of IEEE 802.11p MAC output process for V2X interworking enhancement.
IET Networks, 2018

A Novel Heterogeneous Approximate Multiplier for Low Power and High Performance.
Embedded Systems Letters, 2018

QoS-Based Sequential Detection Algorithm for Jamming Attacks in VANET.
Proceedings of the Future Network Systems and Security - 4th International Conference, 2018

Rapid in-memory matrix multiplication using associative processor.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
AS8-static random access memory (SRAM): asymmetric SRAM architecture for soft error hardening enhancement.
IET Circuits, Devices & Systems, 2017

Sensing user context and habits for run-time energy optimization.
EURASIP J. Emb. Sys., 2017

Two stage particle swarm optimization to solve the flexible job shop predictive scheduling problem considering possible machine breakdowns.
Computers & Industrial Engineering, 2017

A New Rescheduling Heuristic for Flexible Job Shop Problem with Machine Disruption.
Proceedings of the Service Orientation in Holonic and Multi-Agent Manufacturing, 2017

Adaptive video-based algorithm for accident detection on highways.
Proceedings of the 12th IEEE International Symposium on Industrial Embedded Systems, 2017

Stochastic modeling of IEEE 802.11p output process for efficient V2X large-scale interworking.
Proceedings of the 24. IEEE Symposium on Communications and Vehicular Technology, 2017

Hardware resource estimation for heterogeneous FPGA-based SoCs.
Proceedings of the Symposium on Applied Computing, 2017

A Rapid Data Communication Exploration Tool for Hybrid CPU-FPGA Architectures.
Proceedings of the 25th Euromicro International Conference on Parallel, 2017

Reconfigurable Hardened Latch and Flip-Flop for FPGAs.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

An Energy-Aware Learning Agent for Power Management in Mobile Devices.
Proceedings of the Advances in Artificial Intelligence: From Theory to Practice, 2017

User model-based method for IEEE 802.11p performance evaluation in vehicular safety applications.
Proceedings of the 2017 IEEE International Conference on Vehicular Electronics and Safety, 2017

Adaptive Reliability for Fault Tolerant Multicore Systems.
Proceedings of the Euromicro Conference on Digital System Design, 2017

Design Space exploration of FPGA-based accelerators with multi-level parallelism.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Real-Time Multi-Scale Pedestrian Detection for Driver Assistance Systems.
Proceedings of the 54th Annual Design Automation Conference, 2017

Performance Exploration of AMBA AXI4 Bus Protocols for Wireless Sensor Networks.
Proceedings of the 14th IEEE/ACS International Conference on Computer Systems and Applications, 2017

2016
Design of Multiple-Target Tracking System on Heterogeneous System-on-Chip Devices.
IEEE Trans. Vehicular Technology, 2016

EQUITAS: A tool-chain for functional safety and reliability improvement in automotive systems.
Microprocessors and Microsystems - Embedded Hardware Design, 2016

A co-design space exploration tool for avionic high performance heterogeneous embedded architectures.
Proceedings of the 11th International Design & Test Symposium, 2016

Using IoT in breakdown tolerance: PSO solving FJSP.
Proceedings of the 11th International Design & Test Symposium, 2016

Keynote 2: "Embedded systems design for critical applications".
Proceedings of the 11th International Design & Test Symposium, 2016

A comparison and performance evaluation of FPGA soft-cores for embedded multi-core systems.
Proceedings of the 11th International Design & Test Symposium, 2016

Adaptive routing framework for network on chip architectures.
Proceedings of the 2016 Workshop on Rapid Simulation and Performance Evaluation, 2016

Register file reliability enhancement through adjacent narrow-width exploitation.
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

Device Context Classification for Mobile Power Consumption Reduction.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

NS-SRAM: Neighborhood Solidarity SRAM for Reliability Enhancement of SRAM Memories.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Auto-tuning Fault Tolerance Technique for DSP-Based Circuits in Transportation Systems.
Proceedings of the 1st International Workshop on RESource Awareness and Application Auto-tuning in Adaptive and heterogeNeous compuTing co-located with 19th International Conference on Design, 2016

Lin-analyzer: a high-level performance analysis tool for FPGA-based accelerators.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Scalable row-based parallel H.264 decoder on embedded multicore processors.
Signal, Image and Video Processing, 2015

Customizing VLIW processors from dynamically profiled execution traces.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

Hardware resource utilization optimization in FPGA-based Heterogeneous MPSoC architectures.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

Framework for a Selection of Custom Instructions for Ht-MPSoC in Area-performance Aware Manner.
Embedded Systems Letters, 2015

A multi-objective approach for software/hardware partitioning in a multi-target tracking system.
Proceedings of the 2015 International Symposium on Rapid System Prototyping, 2015

A bi-objective heuristic for heterogeneous MPSoC design space exploration.
Proceedings of the 10th International Design & Test Symposium, 2015

Heterogeneous multi-core architecture for a 4G communication in high-speed railway.
Proceedings of the 10th International Design & Test Symposium, 2015

Modeling transistor level masking of soft errors in combinational circuits.
Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015

Enhanced Quality Using Intensive Test and Analysis on Simulators.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Application Sequence Prediction for Energy Consumption Reduction in Mobile Systems.
Proceedings of the 15th IEEE International Conference on Computer and Information Technology, 2015

2014
System-level power estimation tool for embedded processor based platforms.
Proceedings of the 2014 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2014

PETS: Power and energy estimation tool at system-level.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

A dynamically reconfigurable architecture for emergency and disaster management in ITS.
Proceedings of the International Conference on Connected Vehicles and Expo, 2014

Design space exploration of multiple loops on FPGAs using high level synthesis.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

MIPT: Rapid exploration and evaluation for migrating sequential algorithms to multiprocessing systems with multi-port memories.
Proceedings of the International Conference on High Performance Computing & Simulation, 2014

Application specific multi-port memory customization in FPGAs.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

A mixed integer linear programming approach for design space exploration in FPGA-based MPSoC.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

HOG Feature Extractor Hardware Accelerator for Real-Time Pedestrian Detection.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Design Space Exploration for Customized Asymmetric Heterogeneous MPSoC.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Fast System Level Benchmarks for Multicore Architectures.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

ARABICA: A Reconfigurable Arithmetic Block for ISA Customization.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013
Special issue DSD 2012 on Reliability and dependability in MPSoC Technologies.
Microprocessors and Microsystems - Embedded Hardware Design, 2013

A survey of cross-layer power-reliability tradeoffs in multi and many core systems-on-chip.
Microprocessors and Microsystems - Embedded Hardware Design, 2013

Two-level caches tuning technique for energy consumption in reconfigurable embedded MPSoC.
Journal of Systems Architecture - Embedded Systems Design, 2013

Shared hardware accelerator architectures for heterogeneous MPSoCs.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

Efficient FPGA implementation of H.264 CAVLC entropy decoder.
Proceedings of the 8th International Design and Test Symposium, 2013

Compilation optimization exploration for thermal dissipation reduction in embedded systems.
Proceedings of the 8th International Design and Test Symposium, 2013

Energy consumption in reconfigurable mpsoc architecture: Two-level caches optimization oriented approach.
Proceedings of the 8th International Design and Test Symposium, 2013

Radar signature in multiple target tracking system for driver assistant application.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
A fast MPSoC virtual prototyping for intensive signal processing applications.
Microprocessors and Microsystems - Embedded Hardware Design, 2012

Parity-based mono-Copy Cache for low power consumption and high reliability.
Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping, 2012

Performance evaluation of a flow control algorithm for Network-on-Chip.
Proceedings of the 2012 International Conference on High Performance Computing & Simulation, 2012

An efficient power estimation methodology for complex RISC processor-based platforms.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

H.264 Macroblock Line Level Parallel Video Decoding on Embedded Multicore Processors.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Concurrent Phase Classification for Accelerating MPSoC Simulation.
Proceedings of the ARCS 2012 Workshops, 28. Februar - 2. März 2012, München, Germany, 2012

2011
Performance evaluation and design tradeoffs of on-chip interconnect architectures.
Simulation Modelling Practice and Theory, 2011

Embedded architecture with hardware accelerator for target recognition in driver assistance system.
SIGARCH Computer Architecture News, 2011

Dynamically reconfigurable architecture for a driver assistant system.
Proceedings of the IEEE 9th Symposium on Application Specific Processors, 2011

Hybrid system level power consumption estimation for FPGA-based MPSoC.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Fast and accurate hybrid power estimation methodology for embedded systems.
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011

2010
Parallel application sampling for accelerating MPSoC simulation.
Design Autom. for Emb. Sys., 2010

An Improved Automotive Multiple Target Tracking System Design.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

H.264 Color Components Video Decoding Parallelization on Multi-core Processors.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009
Power-Aware Bus Coscheduling for Periodic Realtime Applications Running on Multiprocessor SoC.
Trans. HiPEAC, 2009

A reconfigurable platform architecture for an automotive multiple-target tracking system.
SIGBED Review, 2009

Trade-Off Exploration for Target Tracking Application in a Customized Multiprocessor Architecture.
EURASIP J. Emb. Sys., 2009

Driver assistance system design and its optimization for FPGA based MPSoC.
Proceedings of the IEEE 7th Symposium on Application Specific Processors, 2009

A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008
Multi-granularity sampling for simulating concurrent heterogeneous applications.
Proceedings of the 2008 International Conference on Compilers, 2008

An MPSoC architecture for the Multiple Target Tracking application in driver assistant system.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

2007
Multilevel MPSOC simulation using an MDE approach.
Proceedings of the 2007 IEEE International SOC Conference, 2007

An MPSoC Performance Estimation Framework Using Transaction Level Modeling.
Proceedings of the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), 2007

Adaptive Sampling for Efficient MPSoC Architecture Simulation.
Proceedings of the 15th International Symposium on Modeling, 2007

2006
Pattern-driven prefetching for multimedia applications on embedded processors.
Journal of Systems Architecture, 2006

A Real Time Signal Processing for an Anticollision Road Radar System.
Proceedings of the 64th IEEE Vehicular Technology Conference, 2006

Rapid Performance and Power Consumption Estimation Methods for Embedded System Design.
Proceedings of the 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 2006

A Low Speed Digital Correlator Architecture Optimized For Resource Savings.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

Adapting EPIC Architecture's Register Stack for Virtual Stack Machines.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Estimating Energy Consumption for an MPSoC Architectural Exploration.
Proceedings of the Architecture of Computing Systems, 2006

2005
Optimal sample length for efficient cache simulation.
Journal of Systems Architecture, 2005

2004
An automatic communication synthesis for high level SOC desing using transaction level modelling (poster).
Proceedings of the Forum on specification and Design Languages, 2004

Adaptive Prefetching for Multimedia Applications in Embedded Systems.
Proceedings of the 2004 Design, 2004

2003
Comparing Multiported Cache Schemes.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003

Impact of Code Compression on the Power Consumption in Embedded Systems.
Proceedings of the International Conference on Embedded Systems and Applications, 2003

2001
Performances of a Dynamic Threads Scheduler.
Proceedings of the Euro-Par 2001: Parallel Processing, 2001

1999
A Simulator for a Multithreaded Processor.
Proceedings of the 17th IASTED International Conference on Applied Informatics, 1999

1997
A Parallel Tabu Search Algorithm For The 0-1 Multidimensional Knapsack Problem.
Proceedings of the 11th International Parallel Processing Symposium (IPPS '97), 1997


  Loading...