Yuan Taur

Affiliations:
  • University of California, San Diego, USA


According to our database1, Yuan Taur authored at least 11 papers between 1995 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 1998, "For outstanding contributions to advanced CMOS technology.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2014
Determination of energy and spatial distribution of oxide border traps in In<sub>0.53</sub>Ga<sub>0.47</sub>As MOS capacitors from capacitance-voltage characteristics measured at various temperatures.
Microelectron. Reliab., 2014

2010
Compact modeling of quantum effects in symmetric double-gate MOSFETs.
Microelectron. J., 2010

2009
A Review on Compact Modeling of Multiple-Gate MOSFETs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

2008
Compact modeling of multiple-gate MOSFETs.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2001
Device scaling limits of Si MOSFETs and their application dependencies.
Proc. IEEE, 2001

Transistors and IC design.
Adv. Comput., 2001

1999
Modeling and characterization of quantization, polysilicon depletion, and direct tunneling effects in MOSFETs with ultrathin oxides.
IBM J. Res. Dev., 1999

1998
4- and 13-GHz tuned amplifiers implemented in a 0.1-μm CMOS technology on SOI, SOS, and bulk substrates.
IEEE J. Solid State Circuits, 1998

1997
CMOS scaling into the nanometer regime.
Proc. IEEE, 1997

1995
CMOS scaling into the 21st century: 0.1 µm and beyond.
IBM J. Res. Dev., 1995

A half-micron CMOS logic generation.
IBM J. Res. Dev., 1995


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