Wantong Li
Orcid: 0000-0002-8288-393X
According to our database1,
Wantong Li
authored at least 27 papers
between 2018 and 2024.
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Bibliography
2024
NeuroSim V1.4: Extending Technology Support for Digital Compute-in-Memory Toward 1nm Node.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024
2023
H3DAtten: Heterogeneous 3-D Integrated Hybrid Analog and Digital Compute-in-Memory Accelerator for Vision Transformer Self-Attention.
IEEE Trans. Very Large Scale Integr. Syst., October, 2023
Temporal Frame Filtering for Autonomous Driving Using 3D-Stacked Global Shutter CIS With IWO Buffer Memory and Near-Pixel Compute.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023
ENNA: An Efficient Neural Network Accelerator Design Based on ADC-Free Compute-In-Memory Subarrays.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023
A Reconfigurable Monolithic 3D Switched-Capacitor DC-DC Converter with Back-End-of-Line Oxide Channel Transistor.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
RAWAtten: Reconfigurable Accelerator for Window Attention in Hierarchical Vision Transformers.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Enabling Ultra-Low Power Ultrasound Imaging with Compute-in-Memory Sparse Reconstruction Accelerator.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023
Optimization Strategies for Digital Compute-in-Memory from Comparative Analysis with Systolic Array.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References.
IEEE J. Solid State Circuits, 2022
MAC-ECC: In-Situ Error Correction and Its Design Methodology for Reliable NVM-Based Compute-in-Memory Inference Engine.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
IEEE Des. Test, 2022
A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation between Sub-arrays.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A Method for Reverse Engineering Neural Network Parameters from Compute-in-Memory Accelerators.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
A 40nm RRAM Compute-in-Memory Macro with Parallelism-Preserving ECC for Iso-Accuracy Voltage Scaling.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
Secure XOR-CIM Engine: Compute-In-Memory SRAM Architecture With Embedded XOR Encryption.
IEEE Trans. Very Large Scale Integr. Syst., 2021
NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark.
Frontiers Artif. Intell., 2021
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021
A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021
Secure-RRAM: A 40nm 16kb Compute-in-Memory Macro with Reconfigurability, Sparsity Control, and Embedded Security.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
2020
Automatic Method for Extraction of Complex Road Intersection Points From High-Resolution Remote Sensing Images Based on Fuzzy Inference.
IEEE Access, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
2019
Remote. Sens., 2019
2018
Proceedings of the IEEE International Conference on RFID Technology & Application, 2018
Improved Ant Colony Optimization Algorithm for Optimized Nodes Deployment of HAP-Based Marine Monitoring Sensor Networks.
Proceedings of the Communications, Signal Processing, and Systems, 2018