Sheldon X.-D. Tan

According to our database1, Sheldon X.-D. Tan authored at least 235 papers between 1997 and 2019.

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Bibliography

2019
EM-Aware and Lifetime-Constrained Optimization for Multisegment Power Grid Networks.
IEEE Trans. VLSI Syst., 2019

Saturation-Volume Estimation for Multisegment Copper Interconnect Wires.
IEEE Trans. VLSI Syst., 2019

GDP: A Greedy Based Dynamic Power Budgeting Method for Multi/Many-Core Systems in Dark Silicon.
IEEE Trans. Computers, 2019

Reliability based hardware Trojan design using physics-based electromigration models.
Integration, 2019

GPU-based Ising Computing for Solving Balanced Min-Cut Graph Partitioning Problem.
CoRR, 2019

GLU3.0: Fast GPU-based Parallel Sparse LU Factorization for Circuit Simulation.
CoRR, 2019

Dynamic Reliability Management for Multi-Core Processor Based on Deep Reinforcement Learning.
Proceedings of the 16th International Conference on Synthesis, 2019

Long-Term Reliability Management For Multitasking GPGPUs.
Proceedings of the 16th International Conference on Synthesis, 2019

Hot Spot Identification and System Parameterized Thermal Modeling for Multi-Core Processors Through Infrared Thermal Imaging.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Postvoiding FEM Analysis for Electromigration Failure Characterization.
IEEE Trans. VLSI Syst., 2018

Recovery-Aware Proactive TSV Repair for Electromigration Lifetime Enhancement in 3-D ICs.
IEEE Trans. VLSI Syst., 2018

Physics-Based Compact TDDB Models for Low-k BEOL Copper Interconnects With Time-Varying Voltage Stressing.
IEEE Trans. VLSI Syst., 2018

Fast Electromigration Stress Evolution Analysis for Interconnect Trees Using Krylov Subspace Method.
IEEE Trans. VLSI Syst., 2018

Thermal-Sensor-Based Occupancy Detection for Smart Buildings Using Machine-Learning Methods.
ACM Trans. Design Autom. Electr. Syst., 2018

Fast Electromigration Immortality Analysis for Multisegment Copper Interconnect Wires.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

A Fast Leakage-Aware Full-Chip Transient Thermal Estimation Method.
IEEE Trans. Computers, 2018

Dynamic reliability management based on resource-based EM modeling for multi-core microprocessors.
Microelectronics Journal, 2018

Recent advances in EM and BTI induced reliability modeling, analysis and optimization (invited).
Integration, 2018

Detection of counterfeited ICs via on-chip sensor and post-fabrication authentication policy.
Integration, 2018

DEEPEYE: A Compact and Accurate Video Comprehension at Terminal Devices Compressed with Quantization and Tensorization.
CoRR, 2018

Accelerating Electromigration Wear-Out Effects Based on Configurable Sink-Structured Wires.
Proceedings of the 15th International Conference on Synthesis, 2018

Reliability Based Hardware Trojan Design Using Physics-Based Electromigration Models.
Proceedings of the 15th International Conference on Synthesis, 2018

Prediction of chaotic time series by using ANNs, ANFIS and SVMs.
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

Electronic System for Chaotic Time Series Prediction Associated to Human Disease.
Proceedings of the IEEE International Conference on Healthcare Informatics, 2018

Multi-physics-based FEM analysis for post-voiding analysis of electromigration failure effects.
Proceedings of the International Conference on Computer-Aided Design, 2018

Electromigration-lifetime constrained power grid optimization considering multi-segment interconnect wires.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Accelerating electromigration aging for fast failure detection for nanometer ICs.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Energy and Lifetime Optimizations for Dark Silicon Manycore Microprocessor Considering Both Hard and Soft Errors.
IEEE Trans. VLSI Syst., 2017

Editorial.
IEEE Trans. VLSI Syst., 2017

Dynamic electromigration modeling for transient stress evolution and recovery under time-dependent current and temperature stressing.
Integration, 2017

Comprehensive detection of counterfeit ICs via on-chip sensor and post-fabrication authentication policy.
Proceedings of the 14th International Conference on Synthesis, 2017

Prediction of chaotic time-series with different MLE values using FPGA-based ANNs.
Proceedings of the 14th International Conference on Synthesis, 2017

Fast physics-based electromigration analysis for multi-branch interconnect trees.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Leveraging recovery effect to reduce electromigration degradation in power/ground TSV.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Recovery-aware proactive TSV repair for electromigration in 3D ICs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Physics-based electromigration modeling and assessment for multi-segment interconnects in power grid networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Dynamic temperature-aware reliability modeling for multi-branch interconnect trees.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

Fast two-dimensional finite element analysis for power network DC integrity checks of PCBs.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
GPU-Accelerated Parallel Sparse LU Factorization Method for Fast Circuit Analysis.
IEEE Trans. VLSI Syst., 2016

Corrections to "GPU-Accelerated Parallel Sparse LU Factorization Method for Fast Circuit Analysis".
IEEE Trans. VLSI Syst., 2016

Statistical Rare-Event Analysis and Parameter Guidance by Elite Learning Sample Selection.
ACM Trans. Design Autom. Electr. Syst., 2016

Hierarchical Dynamic Thermal Management Method for High-Performance Many-Core Microprocessors.
ACM Trans. Design Autom. Electr. Syst., 2016

Physics-Based Electromigration Models and Full-Chip Assessment for Power Grid Networks.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Analytical Modeling and Characterization of Electromigration Effects for Multibranch Interconnect Trees.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Editorial: Special Issue on The 14th International Conference on Computer-Aided Design and Computer Graphics (CAD/Graphics 2015).
Integration, 2016

Electromigration assessment for power grid networks considering temperature and thermal stress effects.
Integration, 2016

Parallel GMRES solver for fast analysis of large linear dynamic systems on GPU platforms.
Integration, 2016

EM-Based On-Chip Aging Sensor for Detection of Recycled ICs.
IEEE Design & Test, 2016

New power budgeting and thermal management scheme for multi-core systems in dark silicon.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Finite difference method for electromigration analysis of multi-branch interconnects.
Proceedings of the 13th International Conference on Synthesis, 2016

Online Unusual Behavior Detection for Temperature Sensor Networks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Fast stress analysis for runtime reliability enhancement of 3D IC using artificial neural network.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Learning-based occupancy behavior detection for smart buildings.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Overview of cyber-physical temperature estimation in smart buildings: From modeling to measurements.
Proceedings of the IEEE Conference on Computer Communications Workshops, 2016

Voltage-based electromigration immortality check for general multi-branch interconnects.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Dynamic reliability management for near-threshold dark silicon processors.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Learning-based dynamic reliability management for dark silicon processor considering EM effects.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Invited - Cross-layer modeling and optimization for electromigration induced reliability.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Physics-based full-chip TDDB assessment for BEOL interconnects.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Thermal modeling for energy-efficient smart building with advanced overfitting mitigation technique.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

Electromigration recovery modeling and analysis under time-dependent current and temperature stressing.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Parallel Thermal Analysis of 3-D Integrated Circuits With Liquid Cooling on CPU-GPU Platforms.
IEEE Trans. VLSI Syst., 2015

A GPU-Accelerated Parallel Shooting Algorithm for Analysis of Radio Frequency and Microwave Integrated Circuits.
IEEE Trans. VLSI Syst., 2015

Task Migrations for Distributed Thermal Management Considering Transient Effects.
IEEE Trans. VLSI Syst., 2015

H-Matrix-Based Finite-Element-Based Thermal Analysis for 3D ICs.
ACM Trans. Design Autom. Electr. Syst., 2015

H2-matrix-based finite element linear solver for fast transient thermal analysis of high-performance ICs.
I. J. Circuit Theory and Applications, 2015

Statistical rare event analysis using smart sampling and parameter guidance.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

Rare event diagnosis by iterative failure region locating and elite learning sample selection.
Proceedings of the 16th Latin-American Test Symposium, 2015

Learning Based Compact Thermal Modeling for Energy-Efficient Smart Building Management: (invited).
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

EM-Based on-Chip Aging Sensor for Detection and Prevention of Counterfeit and Recycled ICs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

From Robust Chip to Smart Building: CAD Algorithms and Methodologies for Uncertainty Analysis of Building Performance.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Interconnect reliability modeling and analysis for multi-branch interconnect trees.
Proceedings of the 52nd Annual Design Automation Conference, 2015

GPU-accelerated parallel Monte Carlo analysis of analog circuits by hierarchical graph-based solver.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

New electromigration modeling and analysis considering time-varying temperature and current densities.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Compact Lateral Thermal Resistance Model of TSVs for Fast Finite-Difference Based Thermal Analysis of 3-D Stacked ICs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Compact thermal modeling for packaged microprocessor design with practical power maps.
Integration, 2014

Direct finite-element-based solver for 3D-IC thermal analysis via H-matrix representation.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

IR-drop based electromigration assessment: parametric failure chip-scale analysis.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Lifetime optimization for real-time embedded systems considering electromigration effects.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Battery Management and Application for Energy-Efficient Buildings.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Physics-based Electromigration Assessment for Power Grid Networks.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Time-domain performance bound analysis for analog and interconnect circuits considering process variations.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Hybrid dynamic thermal management method with model predictive control.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
Symbolic Moment Computation for Statistical Analysis of Large Interconnect Networks.
IEEE Trans. VLSI Syst., 2013

Composable thermal modeling and simulation for architecture-level thermal designs of multicore microprocessors.
ACM Trans. Design Autom. Electr. Syst., 2013

Performance bound analysis of analog circuits in frequency- and time-domain considering process variations.
ACM Trans. Design Autom. Electr. Syst., 2013

Statistical full-chip total power estimation considering spatially correlated process variations.
Integration, 2013

Parallel power grid analysis using preconditioned GMRES solver on CPU-GPU platforms.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Compact lateral thermal resistance modeling and characterization for TSV and TSV array.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

A power-driven thermal sensor placement algorithm for dynamic thermal management.
Proceedings of the Design, Automation and Test in Europe, 2013

Dynamic thermal management for multi-core microprocessors considering transient thermal effects.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Compact nonlinear thermal modeling of packaged integrated systems.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Performance bound and yield analysis for analog circuits under process variations.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Distributed task migration for thermal hot spot reduction in many-core microprocessors.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
Decentralized and Passive Model Order Reduction of Linear Networks With Massive Ports.
IEEE Trans. VLSI Syst., 2012

General Parameterized Thermal Modeling for High-Performance Microprocessor Design.
IEEE Trans. VLSI Syst., 2012

Compact Modeling of Interconnect Circuits over Wide Frequency Band by Adaptive Complex-Valued Sampling Method.
ACM Trans. Design Autom. Electr. Syst., 2012

Fast Statistical Full-Chip Leakage Analysis for Nanometer VLSI Systems.
ACM Trans. Design Autom. Electr. Syst., 2012

A Fast Non-Monte-Carlo Yield Analysis and Optimization by Stochastic Orthogonal Polynomials.
ACM Trans. Design Autom. Electr. Syst., 2012

Fast timing analysis of clock networks considering environmental uncertainty.
Integration, 2012

Localized relaxation theory of circuits and its applications in electro-thermal analyses.
SCIENCE CHINA Information Sciences, 2012

Symbolic nodal analysis of analog integrated circuits using pathological elements.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

Transient analysis of large linear dynamic networks on hybrid GPU-multicore platforms.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

A new voltage binning technique for yield improvement based on graph theory.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Full-chip thermal analysis of 3D ICs with liquid cooling by GPU-accelerated GMRES method.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Runtime power estimator calibration for high-performance microprocessors.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A GPU-accelerated envelope-following method for switching power converter simulation.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Parallel statistical analysis of analog circuits by GPU-accelerated graph-based approach.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Time-domain performance bound analysis of analog circuits considering process variations.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs.
Springer, ISBN: 978-1-4614-0787-4, 2012

2011
Pathological Element-Based Active Device Models and Their Application to Symbolic Analysis.
IEEE Trans. on Circuits and Systems, 2011

An efficient statistical chip-level total power estimation method considering process variations with spatial correlation.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Statistical full-chip dynamic power estimation considering spatial correlations.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Full-chip runtime error-tolerant thermal estimation and prediction for practical thermal management.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Compact thermal modeling for package design with practical power maps.
Proceedings of the 2011 International Green Computing Conference and Workshops, 2011

Performance bound analysis of analog circuits considering process variations.
Proceedings of the 48th Design Automation Conference, 2011

A structured parallel periodic Arnoldi shooting algorithm for RF-PSS analysis based on GPU platforms.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Battery state of charge estimation using adaptive subspace identification method.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
Fast Analysis of a Large-Scale Inductive Interconnect by Block-Structure-Preserved Macromodeling.
IEEE Trans. VLSI Syst., 2010

Variational Capacitance Extraction and Modeling Based on Orthogonal Polynomial Method.
IEEE Trans. VLSI Syst., 2010

Parameterized architecture-level dynamic thermal models for multicore microprocessors.
ACM Trans. Design Autom. Electr. Syst., 2010

Passive Rational Interpolation-Based Reduction via Carathéodory Extension for General Systems.
IEEE Trans. on Circuits and Systems, 2010

Statistical modeling and analysis of chip-level leakage power by spectral stochastic method.
Integration, 2010

Statistical analysis of large on-chip power grid networks by variational reduction scheme.
Integration, 2010

Symbolic behavioral modeling of low voltage amplifiers.
Proceedings of the 7th International Conference on Electrical Engineering, 2010

A linear statistical analysis for full-chip leakage power with spatial correlation.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

General switch box modeling and optimization for FPGA routing architectures.
Proceedings of the International Conference on Field-Programmable Technology, 2010

General behavioral thermal modeling and characterization for multi-core microprocessor design.
Proceedings of the Design, Automation and Test in Europe, 2010

A linear algorithm for full-chip statistical leakage power analysis considering weak spatial correlation.
Proceedings of the 47th Design Automation Conference, 2010

A robust periodic arnoldi shooting algorithm for efficient analysis of large-scale RF/MM ICs.
Proceedings of the 47th Design Automation Conference, 2010

A fast analog mismatch analysis by an incremental and stochastic trajectory piecewise linear macromodel.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Efficient model reduction of interconnects via double gramians approximation.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Wideband reduced modeling of interconnect circuits by adaptive complex-valued sampling method.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Efficient power grid integrity analysis using on-the-fly error check and reduction.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Architecture-Level Thermal Characterization for Multicore Microprocessors.
IEEE Trans. VLSI Syst., 2009

Multiple block structure-preserving reduced order modeling of interconnect circuits.
Integration, 2009

Hierarchical Krylov subspace based reduction of large interconnects.
Integration, 2009

Fast Analysis of On-Chip Power Grid Circuits by Extended Truncated Balanced Realization Method.
IEICE Transactions, 2009

Statistical decoupling capacitance allocation by efficient numerical quadrature method.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Localized Statistical 3D Thermal Analysis Considering Electro-Thermal Coupling.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Symbolic formulation method for mixed-mode analog circuits using nullors.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

Decoupling capacitance efficient placement for reducing transient power supply noise.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

An efficient decoupling capacitance optimization using piecewise polynomial models.
Proceedings of the Design, Automation and Test in Europe, 2009

GPU friendly fast Poisson solver for structured power grid network analysis.
Proceedings of the 46th Design Automation Conference, 2009

Fast analysis of nontree-clock network considering environmental uncertainty by parameterized and incremental macromodeling.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Statistical modeling and analysis of chip-level leakage power by spectral stochastic method.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Statistical analysis of on-chip power grid networks by variational extended truncated balanced realization method.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Second-Order Balanced Truncation for Passive-Order Reduction of RLCK Circuits.
IEEE Trans. on Circuits and Systems, 2008

Statistical Analysis of On-Chip Power Delivery Networks Considering Lognormal Leakage Current Variations With Spatial Correlation.
IEEE Trans. on Circuits and Systems, 2008

Random Walk Guided Decap Embedding for Power/Ground Network Optimization.
IEEE Trans. on Circuits and Systems, 2008

Fast Variational Analysis of On-Chip Power Grids by Stochastic Extended Krylov Subspace Method.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

A Fast Architecture-Level Thermal Analysis Method for Runtime Thermal Regulation.
J. Low Power Electronics, 2008

An efficient terminal and model order reduction algorithm.
Integration, 2008

Large scale P/G grid transient simulation using hierarchical relaxed approach.
Integration, 2008

Statistic Analysis of Power/Ground Networks Using Single-Node SOR Method.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Modeling and simulation for on-chip power grid networks by locally dominant Krylov subspace method.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Parameterized transient thermal behavioral modeling for chip multiprocessors.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

FEKIS: a fast architecture-level thermal analyzer for online thermal regulation.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Variational capacitance modeling using orthogonal polynomial method.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

ETBR: Extended Truncated Balanced Realization Method for On-Chip Power Grid Network Analysis.
Proceedings of the Design, Automation and Test in Europe, 2008

DeMOR: decentralized model order reduction of linear networks with massive ports.
Proceedings of the 45th Design Automation Conference, 2008

Architecture-level thermal behavioral characterization for multi-core microprocessors.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Hierarchical Krylov subspace reduced order modeling of large RLC circuits.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Minimum Decoupling Capacitor Insertion in VLSI Power/Ground Supply Networks by Semidefinite and Linear Programs.
IEEE Trans. VLSI Syst., 2007

Efficient power modeling and software thermal sensing for runtime temperature monitoring.
ACM Trans. Design Autom. Electr. Syst., 2007

Pattern-Based Iterative Method for Extreme Large Power/Ground Analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

TermMerg: An Efficient Terminal-Reduction Method for Interconnect Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Partitioning-based decoupling capacitor budgeting via sequence of linear programming.
Integration, 2007

Passive Modeling of Interconnects by Waveform Shaping.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

General Block Structure-Preserving Reduced Order Modeling of Linear Dynamic Circuits.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Improving the reliability of on-chip data caches under process variations.
Proceedings of the 25th International Conference on Computer Design, 2007

Voltage drop reduction for on-chip power delivery considering leakage current variations.
Proceedings of the 25th International Conference on Computer Design, 2007

Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Statistical model order reduction for interconnect circuits considering spatial correlations.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

SBPOR: Second-Order Balanced Truncation for Passive Order Reduction of RLC Circuits.
Proceedings of the 44th Design Automation Conference, 2007

Simultaneous Switching Noise Consideration for Power/Ground Network Optimization.
Proceedings of the 10th International Conference on Computer-Aided Design and Computer Graphics, 2007

Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Passive Interconnect Macromodeling Via Balanced Truncation of Linear Systems in Descriptor Form.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Symbolic Analysis of Analog Circuits By Boolean Logic Operations.
IEEE Trans. on Circuits and Systems, 2006

Power/Ground Network Optimization Considering Decap Leakage Currents.
IEEE Trans. on Circuits and Systems, 2006

Wideband passive multiport model order reduction and realization of RLCM circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Fast Thermal Simulation for Runtime Temperature Tracking and Management.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Time-domain analysis methodology for large-scale RLC circuits and its applications.
Science in China Series F: Information Sciences, 2006

Compact Reduced Order Modeling for Multiple-Port Interconnects.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

High accurate pattern based precondition method for extremely large power/ground grid analysis.
Proceedings of the 2006 International Symposium on Physical Design, 2006

Efficient decoupling capacitor planning via convex programming methods.
Proceedings of the 2006 International Symposium on Physical Design, 2006

Statistical Analysis of Power Grid Networks Considering Lognormal Leakage Current Variations with Spatial Correlation.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

A systematic method for functional unit power estimation in microprocessors.
Proceedings of the 43rd Design Automation Conference, 2006

Efficient early stage resonance estimation techniques for C4 package.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Hierarchical approach to exact symbolic analysis of large analog circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

A general hierarchical circuit modeling and simulation algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

A Fast Delay Computation for the Hybrid Structured Clock Network.
IEICE Transactions, 2005

Efficient Simulation of Power/Ground Networks with Package and Vias.
Proceedings of the Integrated Circuit and System Design, 2005

Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Passive Hierarchical Model Order Reduction and Realization of RLCM Circuits.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Efficient Thermal Simulation for Run-Time Temperature Tracking and Management.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

An efficient method for terminal reduction of interconnect circuits considering delay variations.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Fast thermal simulation for architecture level dynamic thermal management.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation.
Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

Partitioning-based approach to fast on-chip decap budgeting and minimization.
Proceedings of the 42nd Design Automation Conference, 2005

Analysis of buffered hybrid structured clock networks.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

A wideband hierarchical circuit reduction for massively coupled interconnects.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

VLSI on-chip power/ground network optimization considering decap leakage currents.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Relaxed hierarchical power/ground grid analysis.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Efficient approximation of symbolic expressions for analog behavioral modeling and analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery.
Proceedings of the Integrated Circuit and System Design, 2004

Transient Analysis of On-Chip Power Distribution Networks Using Equivalent Circuit Modeling.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

An efficient algorithm for transient and distortion analysis of mildly nonlinear analog circuits.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Behavioural modelling of analog circuits by dynamic semi-symbolic analysis.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Partial random walk for large linear network analysis.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Hierarchical Modeling and Simulation of Large Analog Circuits.
Proceedings of the 2004 Design, 2004

Hierarchical approach to exact symbolic analysis of large analog circuits.
Proceedings of the 41th Design Automation Conference, 2004

Dynamic FPGA routing for just-in-time FPGA compilation.
Proceedings of the 41th Design Automation Conference, 2004

A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Efficient very large scale integration power/ground network sizing based on equivalent circuit modeling.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Balanced multi-level multi-way partitioning of analog integrated circuits for hierarchical symbolic analysis.
Integration, 2003

Advanced Physical Models for Mask Data Verification and Impacts on Physical Layout Synthesis.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

A General S-Domain Hierarchical Network Reduction Algorithm.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Efficient DDD-based term generation algorithm for analog circuit behavioral modeling.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2001
Compact representation and efficient generation of s-expandedsymbolic network functions for computer-aided analog circuit design.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Fast Power/Ground Network Optimization Based on Equivalent Circuit Modeling.
Proceedings of the 38th Design Automation Conference, 2001

2000
Hierarchical symbolic analysis of analog integrated circuits viadeterminant decision diagrams.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

Canonical symbolic analysis of large analog circuits withdeterminant decision diagrams.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

Symbolic circuit-noise analysis and modeling with determinant decision diagrams.
Proceedings of ASP-DAC 2000, 2000

1999
Interpretable Symbolic Small-Signal Characterization of Large Analog Circuits using Determinant Decision Diagrams.
Proceedings of the 1999 Design, 1999

Reliability-Constrained Area Optimization of VLSI Power/Ground Networks via Sequence of Linear Programmings.
Proceedings of the 36th Conference on Design Automation, 1999

Balanced Multi-Level Multi-Way Partitioning of Large Analog Circuits for Hierarchical Symbolic Analysis.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1997
Symbolic analysis of large analog circuits with determinant decision diagrams.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997


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