Sumeet Kumar Gupta

According to our database1, Sumeet Kumar Gupta authored at least 49 papers between 2009 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
TiM-DNN: Ternary In-Memory Accelerator for Deep Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Integrated CAM-RAM Functionality using Ferroelectric FETs.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Polarization-induced Strain-coupled TMD FETs (PS FETs) for Non-Volatile Memory Applications.
Proceedings of the 2020 Device Research Conference, 2020

Ternary Compute-Enabled Memory using Ferroelectric Transistors for Accelerating Deep Neural Networks.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Utilization of Negative-Capacitance FETs to Boost Analog Circuit Performances.
IEEE Trans. Very Large Scale Integr. Syst., 2019

ROBIN: Monolithic-3D SRAM for Enhanced Robustness with In-Memory Computation Support.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Family of Compact Non-Volatile Flip-Flops With Ferroelectric FET.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Design of 2T/Cell and 3T/Cell Nonvolatile Memories with Emerging Ferroelectric FETs.
IEEE Des. Test, 2019

Valley-Coupled-Spintronic Non-Volatile Memories with Compute-In-Memory Support.
CoRR, 2019

Non-volatile Logic and Memory based on Reconfigurable Ferroelectric Transistors.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

Non-Volatile Memory utilizing Reconfigurable Ferroelectric Transistors to enable Differential Read and Energy-Efficient In-Memory Computation.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

2018
Compact 3-D-SRAM Memory With Concurrent Row and Column Data Access Capability Using Sequential Monolithic 3-D Integration.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Symmetric 2-D-Memory Access to Multidimensional Data.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Dual Mode Ferroelectric Transistor based Non-Volatile Flip-Flops for Intermittently-Powered Systems.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires.
Proceedings of the 2018 International Conference on IC Design & Technology, 2018

CTCG: Charge-trap based camouflaged gates for reverse engineering prevention.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

2- Transistor Schmitt Trigger based on 2D Electrostrictive Field Effect Transistors.
Proceedings of the 76th Device Research Conference, 2018

Modeling and Comparative Analysis of Hysteretic Ferroelectric and Anti-ferroelectric FETs.
Proceedings of the 76th Device Research Conference, 2018

Insinhts on the DC Characterization of Ferroelectric Field-Effect-Transistors.
Proceedings of the 76th Device Research Conference, 2018

A Three-Terminal Edge-Triggered Mott Switch.
Proceedings of the 76th Device Research Conference, 2018

Computing with ferroelectric FETs: Devices, models, systems, and applications.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Advancing Nonvolatile Computing With Nonvolatile NCFET Latches and Flip-Flops.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Read-enhanced spin memories augmented by phase transition materials (Invited).
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Improving FPGA Design with Monolithic 3D Integration Using High Dense Inter-Stack Via.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Harnessing ferroelectrics for non-volatile memories and logic.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

In Quest of the Next Information Processing Substrate: Extended Abstract: Invited.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Analysis of Functional Oxide based Selectors for Cross-Point Memories.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Comparative Area and Parasitics Analysis in FinFET and Heterojunction Vertical TFET Standard Cells.
ACM J. Emerg. Technol. Comput. Syst., 2016

Device Circuit Co Design of FEFET Based Logic for Low Voltage Processors.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Ferroelectric Transistor based Non-Volatile Flip-Flop.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

On the potential of correlated materials in the design of spin-based cross-point memories (Invited).
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Exploiting ferroelectric FETs for low-power non-volatile logic-in-memory circuits.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Nonvolatile memory design based on ferroelectric FETs.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
A High-Efficiency Switched-Capacitance HTFET Charge Pump for Low-Input-Voltage Applications.
Proceedings of the 28th International Conference on VLSI Design, 2015

Using Multiple-Input NEMS for Parallel A/D Conversion and Image Processing.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Comparing Energy, Area, Delay Tradeoffs in Going Vertical with CMOS and Asymmetric HTFETs.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Single-Ended and Differential MRAMs Based on Spin Hall Effect: A Layout-Aware Design Perspective.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

COAST: Correlated material assisted STT MRAMs for optimized read operation.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

2014
Independently-Controlled-Gate FinFET 6T SRAM Cell Design for Leakage Current Reduction and Enhanced Read Access Speed.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

2013
Dual pillar spin-transfer torque MRAMs for low power applications.
ACM J. Emerg. Technol. Comput. Syst., 2013

Device-Circuit Co-Optimization for Robust Design of FinFET-Based SRAMs.
IEEE Des. Test, 2013

2012
Low-Power Architecture for Epileptic Seizure Detection Based on Reduced Complexity DWT.
ACM J. Emerg. Technol. Comput. Syst., 2012

High-performance low-energy STT MRAM based on balanced write scheme.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Write-optimized reliable design of STT MRAM.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Layout-aware optimization of stt mrams.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Future cache design using STT MRAMs for improved energy efficiency: devices, circuits and architecture.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2010
Digital Computation in Subthreshold Region for Ultralow-Power Operation: A Device-Circuit-Architecture Codesign Perspective.
Proc. IEEE, 2010

2009
Device/circuit interactions at 22nm technology node.
Proceedings of the 46th Design Automation Conference, 2009


  Loading...