Weidong Yang

Orcid: 0000-0003-3610-2343

Affiliations:

Shanghai Jiao Tong University, Shanghai, China

According to our database¹, Weidong Yang authored at least 7 papers between 2023 and 2026.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

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Bibliography

2026

Viper: An ILP-Based Vectorization Framework for Fully Homomorphic Encryption.

[BibT_eX]

[DOI]

Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025

MACS: A Multidomain Collaborative Adaptive Clock Scheme for Large-Scale Reconfigurable Dataflow Accelerators.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., August, 2025

RVME: An Efficient Matrix Engine Design Based on Matrix Extension of RISC-V.

[BibT_eX]

[DOI]

Proceedings of the 43rd IEEE International Conference on Computer Design, 2025

HEILP: An ILP-Based Scale Management Method for Homomorphic Encryption Compiler.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference, 2025

2024

RecPIM: Efficient In-Memory Processing for Personalized Recommendation Inference Using Near-Bank Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024

2023

ACET: An Adaptive Clock Scheme Exploiting Comprehensive Timing Slack for Reconfigurable Processors.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE International Conference on Computer Design, 2023

An Efficient near-Bank Processing Architecture for Personalized Recommendation System.

[BibT_eX]

[DOI]

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

Weidong Yang

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