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Ang Li

Orcid: 0009-0004-8872-7649

Affiliations:
  • Shanghai Jiao Tong University, Department of Micro-Nano Electronics, China


According to our database1, Ang Li authored at least 5 papers between 2023 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
Signal integrity-aware multi-path design workflow for ultra-large-scale three-dimensional chips: A logic-on-memory stacking case study.
[BibTeX]
[DOI]
Ang Li
,
Jianfei Jiang
,
Naifeng Jing
,
Yanan Sun
,
Zhigang Mao
,
Qin Wang
Microelectron. J., 2026

2025
A Hierarchical 3-D Physical Design Method for Ultralarge-Scale Logic-on-Memory CGRA Chip.
[BibTeX]
[DOI]
Zizheng Dong
,
Shuaipeng Li
,
Weijia Zhu
,
Ang Li
,
Qin Wang
,
Naifeng Jing
,
Weiguang Sheng
,
Jianfei Jiang
,
Zhigang Mao
IEEE Trans. Very Large Scale Integr. Syst., June, 2025

2024
A Comprehensive Dataflow-Mapping Optimization for Fully Pipelined Execution in Spatial Programmable Architecture.
[BibTeX]
[DOI]
Pengyu Liu
,
Ang Li
,
Liyan Chen
,
Jianfei Jiang
,
Qin Wang
,
Zhigang Mao
,
Naifeng Jing
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024

VDA: A Simple but Efficient Virtual-Channel-Based Deadlock Avoidance Scheme for Scalable Chiplet Networks.
[BibTeX]
[DOI]
Duo Yu
,
Ang Li
,
Naifeng Jing
,
Jianfei Jiang
,
Weiguang Sheng
,
Qin Wang
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

2023
ACET: An Adaptive Clock Scheme Exploiting Comprehensive Timing Slack for Reconfigurable Processors.
[BibTeX]
[DOI]
Shuya Ji
,
Weidong Yang
,
Jianfei Jiang
,
Naifeng Jing
,
Weiguang Sheng
,
Ang Li
,
Qin Wang
Proceedings of the 41st IEEE International Conference on Computer Design, 2023


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