Weiguang Sheng

According to our database, Weiguang Sheng authored at least 38 papers between 2008 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

RTMDet-R2: An Improved Real-Time Rotated Object Detector.

Haifeng Xiang, Naifeng Jing, Jianfei Jiang, Hongbo Guo, Weiguang Sheng, Zhigang Mao, Qin Wang

Proceedings of the Pattern Recognition and Computer Vision - 6th Chinese Conference, 2023

ACET: An Adaptive Clock Scheme Exploiting Comprehensive Timing Slack for Reconfigurable Processors.

Shuya Ji, Weidong Yang, Jianfei Jiang, Naifeng Jing, Weiguang Sheng, Ang Li, Qin Wang

Proceedings of the 41st IEEE International Conference on Computer Design, 2023

An Efficient near-Bank Processing Architecture for Personalized Recommendation System.

Yuqing Yang, Weidong Yang, Qin Wang, Naifeng Jing, Jianfei Jiang, Zhigang Mao, Weiguang Sheng

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

ReMap: Reorder Mapping for Multi-level Uneven Distribution on Sparse ReRAM Accelerator.

Zhuo Chen, Zihan Zhang, Jianfei Jiang, Weiguang Sheng, Qin Wang, Naifeng Jing

Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022

An Efficient CNN Accelerator Using Inter-Frame Data Reuse of Videos on FPGAs.

Shengzhao Li, Qin Wang, Jianfei Jiang, Weiguang Sheng, Naifeng Jing, Zhigang Mao

IEEE Trans. Very Large Scale Integr. Syst., 2022

A Low Coupling and Lightweight Algorithm for Ship Detection in Optical Remote Sensing Images.

Guochao Deng, Qin Wang, Jianfei Jiang, Qirun Hong, Naifeng Jing, Weiguang Sheng, Zhigang Mao

IEEE Geosci. Remote. Sens. Lett., 2022

2021

A 3.85-Gb/s 8 × 8 Soft-Output MIMO Detector With Lattice-Reduction-Aided Channel Preprocessing.

Zhuojun Liang, Dongxu Lv, Chao Cui, Hai-Bao Chen, Weifeng He, Weiguang Sheng, Naifeng Jing, Zhigang Mao, Guanghui He

IEEE Trans. Very Large Scale Integr. Syst., 2021

Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture.

Chen Yin, Qin Wang, Jianfei Jiang, Weiguang Sheng, Guanghui He, Zhigang Mao, Naifeng Jing

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Reducing Memory Access Conflicts with Loop Transformation and Data Reuse on Coarse-grained Reconfigurable Architecture.

Yuge Chen, Zhongyuan Zhao, Jianfei Jiang, Guanghui He, Zhigang Mao, Weiguang Sheng

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

A Mapping Method for Reconfigurable Array based on Decoupled DataFlow.

Zihan Zhang, Jianfei Jiang, Weiguang Sheng, Qin Wang, Zhigang Mao, Naifeng Jing

Proceedings of the 7th IEEE International Conference on Big Data Security on Cloud, 2021

2020

Towards Higher Performance and Robust Compilation for CGRA Modulo Scheduling.

Zhongyuan Zhao, Weiguang Sheng, Qin Wang, Wenzhi Yin, Pengfei Ye, Jinchao Li, Zhigang Mao

IEEE Trans. Parallel Distributed Syst., 2020

Priority Branches for Ship Detection in Optical Remote Sensing Images.

Yijia Zhang, Weiguang Sheng, Jianfei Jiang, Naifeng Jing, Qin Wang, Zhigang Mao

Remote. Sens., 2020

Enabling Resistive-RAM-based Activation Functions for Deep Neural Network Acceleration.

Zihan Zhang, Taozhong Li, Ning Guan, Qin Wang, Guanghui He, Weiguang Sheng, Zhigang Mao, Naifeng Jing

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

2019

A New Cellular-Based Redundant TSV Structure for Clustered Faults.

Qin Wang, Zechen Liu, Jianfei Jiang, Naifeng Jing, Weiguang Sheng

IEEE Trans. Very Large Scale Integr. Syst., 2019

Lung Nodule Detection in CT Images Using a Raw Patch-Based Convolutional Neural Network.

Qin Wang, Fengyi Shen, Linyao Shen, Jia Huang, Weiguang Sheng

J. Digit. Imaging, 2019

mRNA: Enabling Efficient Mapping Space Exploration for a Reconfiguration Neural Accelerator.

Zhongyuan Zhao, Hyoukjun Kwon, Sachit Kuhar, Weiguang Sheng, Zhigang Mao, Tushar Krishna

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

2018

Fail-Slow at Scale: Evidence of Hardware Performance Faults in Large Production Systems.

Haryadi S. Gunawi, Riza O. Suminto, Russell Sears, Casey Golliher, Swaminathan Sundararaman, Xing Lin, Tim Emami, Weiguang Sheng, Nematollah Bidokhti, Caitie McCaffrey, Deepthi Srinivasan, Biswaranjan Panda, Andrew Baptist, Gary Grider, Parks M. Fields, Kevin Harms, Robert B. Ross, Andree Jacobson, Robert Ricci, Kirk Webb, Peter Alvaro, H. Birali Runesha, Mingzhe Hao, Huaicheng Li

ACM Trans. Storage, 2018

MBSS: A General Paradigm for Static Schedule for Nested Loops with Dynamic Loop Boundary on CGRAs.

Shuai Xie, Zhongyuan Zhao, Weiguang Sheng, Qin Wang, Zhigang Mao

Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

Fail-Slow at Scale: Evidence of Hardware Performance Faults in Large Production Systems.

Haryadi S. Gunawi, Riza O. Suminto, Russell Sears, Casey Golliher, Swaminathan Sundararaman, Xing Lin, Tim Emami, Weiguang Sheng, Nematollah Bidokhti, Caitie McCaffrey, Gary Grider, Parks M. Fields, Kevin Harms, Robert B. Ross, Andree Jacobson, Robert Ricci, Kirk Webb, Peter Alvaro, H. Birali Runesha, Mingzhe Hao, Huaicheng Li

Proceedings of the 16th USENIX Conference on File and Storage Technologies, 2018

Optimizing the data placement and transformation for multi-bank CGRA computing system.

Zhongyuan Zhao, Yantao Liu, Weiguang Sheng, Tushar Krishna, Qin Wang, Zhigang Mao

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

A static-placement, dynamic-issue framework for CGRA loop accelerator.

Zhongyuan Zhao, Weiguang Sheng, Weifeng He, Zhigang Mao, Zhaoshi Li

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

Parallel SER analysis for combinational and sequential standard cell circuits.

Weiguang Sheng, Jianfei Jiang, Zhigang Mao

Microelectron. J., 2016

Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects.

Jianfei Jiang, Zhigang Mao, Weiguang Sheng, Qin Wang, Weifeng He

J. Circuits Syst. Comput., 2016

2015

Resource-saving compile flow for coarse-grained reconfigurable architectures.

Zhongyuan Zhao, Weiguang Sheng, Naifeng Jing, Weifeng He, Zhigang Mao

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Parasitic Parameters Impacts Investigation on Soft Error Rate by a Circuit Level Framework.

Weiguang Sheng, Zhongyuan Zhao, Zhigang Mao

Proceedings of the 21st IEEE Pacific Rim International Symposium on Dependable Computing, 2015

A contactless testing methodology for pre-bond interposer.

Jianfei Jiang, Weiguang Sheng, Qin Wang, Zhigang Mao

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Designing ARINC653 Partition Constrained Scheduling for Secure Real Time Embedded Avionics.

Xiang Tao, Yongxin Zhu, Yishu Mao, Han Song, Mengyun Liu, Xinyi Liu, Weiguang Sheng, Weiwei Shi

Proceedings of the IEEE 2nd International Conference on Cyber Security and Cloud Computing, 2015

An automatic translation and parallelization system for general purpose reconfigurable processor.

Fengshuo Tian, Weiguang Sheng, Weifeng He

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2013

Delay hidden techniques based on configuration contexts reuse and differential reconfiguration in coarse-grained reconfigurable processor.

Haopeng Liu, Weiguang Sheng, Weifeng He, Zhigang Mao

Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012

A pre-emphasis circuit design for high speed on-chip global interconnect.

Jianfei Jiang, Wei-Guang Sheng, Zhi-Gang Mao, Wei-Feng He

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Pareto Optimal Temporal Partition Methodology for Reconfigurable Architectures Based on Multi-objective Genetic Algorithm.

Weiguang Sheng, Weifeng He, Jianfei Jiang, Zhigang Mao

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

2011

A clock-less transceiver for global interconnect.

Jianfei Jiang, Xu Wang, Wei-Guang Sheng, Wei-Feng He, Zhi-Gang Mao

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Efficient temporal task partition for coarse-grain reconfigurable systems based on Simulated Annealing Genetic Algorithm.

Yifan Zhou, Weiguang Sheng, Xie Liu, Weifeng He, Zhigang Mao

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Automatic compilation flow for a coarse-grained reconfigurable processor.

Hao Wang, Weiguang Sheng, Weifeng He

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2009

Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm.

Weiguang Sheng, Liyi Xiao, Zhigang Mao

Proceedings of the 46th Design Automation Conference, 2009

2008

Versatile and Efficient Techniques for Speeding-Up Circuit Level Simulated Fault-Injection Campaigns.

Weiguang Sheng, Liyi Xiao, Zhigang Mao

Proceedings of the 14th IEEE Pacific Rim International Symposium on Dependable Computing, 2008

A novel soft error sensitivity characterization technique based on simulated fault injection and constrained association analysis.

Weiguang Sheng, Liyi Xiao, Zhigang Mao

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

An Automated Fault Injection Technique Based on VHDL Syntax Analysis and Stratified Sampling.

Weiguang Sheng, Liyi Xiao, Zhigang Mao

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008