Qin Wang

Orcid: 0000-0002-6559-5207

Affiliations:

Shanghai Jiao Tong University, Department of Micro/Nano Electronics, China

According to our database¹, Qin Wang authored at least 59 papers between 2011 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of three.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Bibliography

2024

DeltaGNN: Accelerating Graph Neural Networks on Dynamic Graphs With Delta Updating.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024

3A-ReRAM: Adaptive Activation Accumulation in ReRAM-Based CNN Accelerator.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2024

A novel vehicle collision detection system: Integrating audio-visual fusion for enhanced performance.

[BibT_eX]

[DOI]

Expert Syst. Appl., 2024

A 0.8-ps RMS Precision Period Jitter Measurement Circuit with Offset Reduction.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

A Low-Power and High-Accuracy Approximate Adder for Logarithmic Number System.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

VDA: A Simple but Efficient Virtual-Channel-Based Deadlock Avoidance Scheme for Scalable Chiplet Networks.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

SparGNN: Efficient Joint Feature-Model Sparsity Exploitation in Graph Neural Network Acceleration.

[BibT_eX]

[DOI]

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

Bridge-NDP: Achieving Efficient Communication-Computation Overlap in Near Data Processing with Bridge Architecture.

[BibT_eX]

[DOI]

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023

A Unified Clock-Gated Error Correction Scheme With Three-Phase Latch-Based Pipeline for Energy-Efficient Wide Supply Voltage Range Router.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, October, 2023

BC-MVLiM: A Binary-Compatible Multi-Valued Logic-in-Memory Based on Memristive Crossbars.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023

A Reschedulable Dataflow-SIMD Execution for Increased Utilization in CGRA Cross-Domain Acceleration.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2023

Exploiting bit sparsity in both activation and weight in neural networks accelerators.

[BibT_eX]

[DOI]

Integr., 2023

RTMDet-R2: An Improved Real-Time Rotated Object Detector.

[BibT_eX]

[DOI]

Proceedings of the Pattern Recognition and Computer Vision - 6th Chinese Conference, 2023

ACET: An Adaptive Clock Scheme Exploiting Comprehensive Timing Slack for Reconfigurable Processors.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE International Conference on Computer Design, 2023

Pipeline Balancing for Integrated Mapping in High Performance Spatial Programmable Architecture.

[BibT_eX]

[DOI]

Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

An Efficient near-Bank Processing Architecture for Personalized Recommendation System.

[BibT_eX]

[DOI]

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

An NoC-based CNN Accelerator for Edge Computing.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

High-Performance Genomic Analysis Heterogeneous System Using OpenCL.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

ReMap: Reorder Mapping for Multi-level Uneven Distribution on Sparse ReRAM Accelerator.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022

An Efficient CNN Accelerator Using Inter-Frame Data Reuse of Videos on FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2022

A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2022

A Universal RRAM-Based DNN Accelerator With Programmable Crossbars Beyond MVM Operator.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

A Low Coupling and Lightweight Algorithm for Ship Detection in Optical Remote Sensing Images.

[BibT_eX]

[DOI]

IEEE Geosci. Remote. Sens. Lett., 2022

Hierarchical photoelectric hybrid packet switching network for high-performance computing.

[BibT_eX]

[DOI]

JOCN, 2022

Boosting ReRAM-based DNN by Row Activation Oversubscription.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

Fast FPGA-Based Emulation for ReRAM-Enabled Deep Neural Network Accelerator.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Design of Ternary Logic-in-Memory Based on Memristive Dual-Crossbars.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

A Mapping Method for Reconfigurable Array based on Decoupled DataFlow.

[BibT_eX]

[DOI]

Proceedings of the 7th IEEE International Conference on Big Data Security on Cloud, 2021

2020

Towards Higher Performance and Robust Compilation for CGRA Modulo Scheduling.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2020

Priority Branches for Ship Detection in Optical Remote Sensing Images.

[BibT_eX]

[DOI]

Remote. Sens., 2020

Decoupling the Multi-Rate Dataflow Execution in Coarse-Grained Reconfigurable Array.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Enabling Resistive-RAM-based Activation Functions for Deep Neural Network Acceleration.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Frequency Attention Network: Blind Noise Removal for Real Images.

[BibT_eX]

[DOI]

Proceedings of the Computer Vision - ACCV 2020 - 15th Asian Conference on Computer Vision, Kyoto, Japan, November 30, 2020

2019

A New Cellular-Based Redundant TSV Structure for Clustered Faults.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add Operations.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2019

Energy-Efficient Nonvolatile SRAM Design Based on Resistive Switching Multi-Level Cells.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2019

Scale Adaptive Proposal Network for Object Detection in Remote Sensing Images.

[BibT_eX]

[DOI]

IEEE Geosci. Remote. Sens. Lett., 2019

Lung Nodule Detection in CT Images Using a Raw Patch-Based Convolutional Neural Network.

[BibT_eX]

[DOI]

J. Digit. Imaging, 2019

A Rapid Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A New Approximate Multiplier Design for Digital Signal Processing.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018

IBOM: An Integrated and Balanced On-Chip Memory for High Performance GPGPUs.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2018

MBSS: A General Paradigm for Static Schedule for Nested Loops with Dynamic Loop Boundary on CGRAs.

[BibT_eX]

[DOI]

Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

Optimizing the data placement and transformation for multi-bank CGRA computing system.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

Dynamic data split: A crosstalk suppression scheme in TSV-based 3D IC.

[BibT_eX]

[DOI]

Integr., 2017

An on-chip circuit for timing measurement of SRAM IP.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

A metastability-based true random number generator on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016

Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2016

2015

Design optimization for capacitive-resistively driven on-chip global interconnect.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2015

A contactless testing methodology for pre-bond interposer.

[BibT_eX]

[DOI]

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

A Circuit Design of SMS4 against Chosen Plaintext Attack.

[BibT_eX]

[DOI]

Proceedings of the 11th International Conference on Computational Intelligence and Security, 2015

A crosstalk avoidance scheme based on re-layout of signal TSV.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Fault detection and redundancy design for TSVs in 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2013

Modeling and analysis of signal transmission with Through Silicon Via (TSV) noise coupling.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

TSVs-aware floorplanning for 3D integrated circuit.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012

Group-Based Fast Mode Decision Algorithm for Intra Prediction in HEVC.

[BibT_eX]

[DOI]

Proceedings of the Eighth International Conference on Signal Image Technology and Internet Based Systems, 2012

A Case Study of CPNS Intelligence: Provenance Reasoning over Tracing Cross Contamination in Food Supply Chain.

[BibT_eX]

[DOI]

Proceedings of the 32nd International Conference on Distributed Computing Systems Workshops (ICDCS 2012 Workshops), 2012

2011

Effective multi-standard macroblock prediction VLSI design for reconfigurable multimedia systems.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A new asynchronous delay-insensitive link based on a 1-of-4 LETS code.

[BibT_eX]

[DOI]

Can Wang

Qin Wang

Jianfei Jiang

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Qin Wang

Timeline

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