Weizheng Wang

According to our database, Weizheng Wang authored at least 28 papers between 2011 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

SSA: An Effective Secure Scan Architecture Based on Hidden, Randomly Inserted Keys and PUF.

Weizheng Wang, Zhizhi Wu, Jinhai Chen, Peng Liu, Shuo Cai, Neal N. Xiong

IEEE Internet Things J., July, 2025

Low-Power and High-Speed SRAM Cells With Double-Node Upset Self-Recovery for Reliable Applications.

Shuo Cai, Xinjie Liang, Zhu Huang, Weizheng Wang, Fei Yu

IEEE Trans. Very Large Scale Integr. Syst., February, 2025

2024

DAF: An Effective Design-for-Testability Authorization Framework Based on Obfuscation Mechanisms for Defending Complex Attacks.

Weizheng Wang, Xingxing Gong, Xiangqi Wang, Shuo Cai, Peng Liu, Neal N. Xiong

IEEE Internet Things J., December, 2024

A secure scan architecture using dynamic key to thwart scan-based side-channel attacks.

Weizheng Wang, Jinhai Chen, Xianmin Pan

Microelectron. J., January, 2024

A Low-Overhead and High-Security Scan Design Based on Scan Obfuscation.

Weizheng Wang, Xingxing Gong, Shuo Cai, Jiamin Liu, Xiangqi Wang

IEEE Access, 2024

2023

A secure scan architecture using parallel latch-based lock.

Weizheng Wang, Jian Liang, Xiangqi Wang, Xianmin Pan, Shuo Cai

Integr., November, 2023

Four-input-C-element-based multiple-node-upset-self-recoverable latch designs.

Shuo Cai, Caicai Xie, Yan Wen, Weizheng Wang, Fei Yu, Lairong Yin

Integr., May, 2023

A highly reliable and low-power cross-coupled 18T SRAM cell.

Shuo Cai, Yan Wen, Jiangbiao Ouyang, Weizheng Wang, Fei Yu, Bo Li

Microelectron. J., April, 2023

Low-power and high-speed SRAM cells for double-node-upset recovery.

Shuo Cai, Yan Wen, Caicai Xie, Weizheng Wang, Fei Yu

Integr., 2023

A Low-Delay Quadruple-Node-Upset Self-Recoverable Latch Design.

Shuo Cai, Jiangbiao Ouyang, Yan Wen, Weizheng Wang, Fei Yu

Proceedings of the 32nd IEEE Asian Test Symposium, 2023

2022

Ensuring Cryptography Chips Security by Preventing Scan-Based Side-Channel Attacks With Improved DFT Architecture.

Weizheng Wang, Xiangqi Wang, Jin Wang, Neal N. Xiong, Shuo Cai, Peng Liu

IEEE Trans. Syst. Man Cybern. Syst., 2022

An Accurate Estimation Algorithm for Failure Probability of Logic Circuits Using Correlation Separation.

Shuo Cai, Binyong He, Sicheng Wu, Jin Wang, Weizheng Wang, Fei Yu

J. Electron. Test., 2022

2021

Defect Analysis and Parallel Testing for 3D Hybrid CMOS-Memristor Memory.

Peng Liu, Zhiqiang You, Jigang Wu, Michael Elimu, Weizheng Wang, Shuo Cai, Yinhe Han

IEEE Trans. Emerg. Top. Comput., 2021

A Low-Cost Quadruple-Node-Upset Self-Recoverable Latch Design.

Shuo Cai, Caicai Xie, Yan Wen, Weizheng Wang

Proceedings of the IEEE International Test Conference in Asia, 2021

2020

Soft Error Reliability Evaluation of Nanoscale Logic Circuits in the Presence of Multiple Transient Faults.

Shuo Cai, Binyong He, Weizheng Wang, Peng Liu, Fei Yu, Lairong Yin, Bo Li

J. Electron. Test., 2020

2019

Securing Cryptographic Chips against Scan-Based Attacks in Wireless Sensor Network Applications.

Weizheng Wang, Zhuo Deng, Jin Wang, Arun Kumar Sangaiah, Shuo Cai, Zafer Al-Makhadmeh, Amr Tolba

Sensors, 2019

Enhancing Sensor Network Security with Improved Internal Hardware Design.

Weizheng Wang, Zhuo Deng, Jin Wang

Sensors, 2019

A word-frequency-preserving steganographic method based on synonym substitution.

Lingyun Xiang, Xiao Yang, Jiahe Zhang, Weizheng Wang

Int. J. Comput. Sci. Eng., 2019

Single Event Transient Propagation Probabilities Analysis for Nanometer CMOS Circuits.

Shuo Cai, Weizheng Wang, Fei Yu, Binyong He

J. Electron. Test., 2019

A Secure DFT Architecture Protecting Crypto Chips Against Scan-Based Attacks.

Weizheng Wang, Jincheng Wang, Wei Wang, Peng Liu, Shuo Cai

IEEE Access, 2019

2018

Defect Analysis and Parallel March Test Algorithm for 3D Hybrid CMOS-Memristor Memory.

Peng Liu, Jigang Wu, Zhiqiang You, Michael Elimu, Weizheng Wang, Shuo Cai

Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017

Reliability evaluation of logic circuits based on transient faults propagation metrics.

Shuo Cai, Fei Yu, Weizheng Wang, Tieqiao Liu, Peng Liu, Wei Wang

IEICE Electron. Express, 2017

2016

A 2.7 GHz Low-Phase-Noise LC-QVCO Using the Gate-Modulated Coupling Technique.

Fei Yu, Qiang Tang, Weizheng Wang, Honglin Wu

Wirel. Pers. Commun., 2016

2015

Logic operation-based DFT method and 1R memristive crossbar March-like test algorithm.

Peng Liu, Zhiqiang You, Jishun Kuang, Zhipeng Hu, Weizheng Wang

IEICE Electron. Express, 2015

2013

Low power logic BIST with high test effectiveness.

Weizheng Wang, Peng Liu, Shuo Cai, Lingyun Xiang

IEICE Electron. Express, 2013

2012

A scan disabling-based BAST scheme for test cost and test power reduction.

Zhiqiang You, Weizheng Wang, Peng Liu, Jishun Kuang, Zheng Qin

IEICE Electron. Express, 2012

Switching activity reduction for scan-based BIST using weighted scan input data.

Weizheng Wang, Jishun Kuang, Peng Liu, Xin Peng, Zhiqiang You

IEICE Electron. Express, 2012

2011

A scan disabling-based BAST scheme for test cost reduction.

Zhiqiang You, Weizheng Wang, Zhiping Dou, Peng Liu, Jishun Kuang

IEICE Electron. Express, 2011