Shuo Cai

According to our database1, Shuo Cai authored at least 22 papers between 2013 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




A 1 V, 0.53 ns, 59 μW Current Comparator Using Standard 0.18 μm CMOS Technology.
Wirel. Pers. Commun., 2020

Soft Error Reliability Evaluation of Nanoscale Logic Circuits in the Presence of Multiple Transient Faults.
J. Electron. Test., 2020

Secure Communication Scheme Based on a New 5D Multistable Four-Wing Memristive Hyperchaotic System with Disturbance Inputs.
Complex., 2020

CCII and FPGA Realization: A Multistable Modified Fourth-Order Autonomous Chua's Chaotic System with Coexisting Multiple Attractors.
Complex., 2020

Dynamic Analysis, Circuit Design, and Synchronization of a Novel 6D Memristive Four-Wing Hyperchaotic System with Multiple Coexisting Attractors.
Complex., 2020

Chaos-Based Application of a Novel Multistable 5D Memristive Hyperchaotic System with Coexisting Multiple Attractors.
Complex., 2020

Securing Cryptographic Chips against Scan-Based Attacks in Wireless Sensor Network Applications.
Sensors, 2019

A robust and fixed-time zeroing neural dynamics for computing time-variant nonlinear equation using a novel nonlinear activation function.
Neurocomputing, 2019

Single Event Transient Propagation Probabilities Analysis for Nanometer CMOS Circuits.
J. Electron. Test., 2019

Analysis and FPGA Realization of a Novel 5D Hyperchaotic Four-Wing Memristive System, Active Control Synchronization, and Secure Communication Application.
Complex., 2019

Design and FPGA Implementation of a Pseudorandom Number Generator Based on a Four-Wing Memristive Hyperchaotic System and Bernoulli Map.
IEEE Access, 2019

A Secure DFT Architecture Protecting Crypto Chips Against Scan-Based Attacks.
IEEE Access, 2019

A Semantic Segmentation Approach Based on DeepLab Network in High-Resolution Remote Sensing Images.
Proceedings of the Image and Graphics - 10th International Conference, 2019

Defect Analysis and Parallel March Test Algorithm for 3D Hybrid CMOS-Memristor Memory.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

A novel test data compression approach based on bit reversion.
IEICE Electron. Express, 2017

Reliability evaluation of logic circuits based on transient faults propagation metrics.
IEICE Electron. Express, 2017

A parallel-SSHI rectifier for ultra-low-voltage piezoelectric vibration energy harvesting.
IEICE Electron. Express, 2016

The Design of Augmented Reality-Based Learning System Applied in U-Learning Environment.
Proceedings of the E-Learning and Games - 10th International Conference, 2016

An efficient small-delay faults simulator based on critical path tracing.
Int. J. Circuit Theory Appl., 2015

Harzard-Based ATPG for Improving Delay Test Quality.
J. Electron. Test., 2015

BEE OS: Supporting Batch Execution with a Preemptive Real-Time Kernel.
Proceedings of the Advances in Wireless Sensor Networks - The 8th China Conference, 2014

Low power logic BIST with high test effectiveness.
IEICE Electron. Express, 2013