Bo Li

Orcid: 0000-0003-4905-2744

Affiliations:
  • Chinese Academy of Sciences, Institute of Microelectronics, Beijing, China
  • INSA Lyon, Ampere Lab, Villeurbanne, France (PhD 2012)


According to our database1, Bo Li authored at least 23 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
A Novel Reliability-Enhanced Dual Over-Temperature Protection Circuit With Delayed Thermal Restart for Power ICs.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

2023
An on-chip integrated current sensor with high precision and large current range for smart power ICs.
Microelectron. J., April, 2023

Novel SenseFET structure for VDMOS with adopting body reverse bias technique to adjust the reference current ratio.
Microelectron. J., April, 2023

A highly reliable and low-power cross-coupled 18T SRAM cell.
Microelectron. J., April, 2023

The Effects of $\gamma$ Radiation-Induced Trapped Charges on Single Event Transient in DSOI Technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2023

2022
Design and Experimentation of Inductorless Low-Pass NGD Integrated Circuit in 180-nm CMOS Technology.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Single Event Induced Crosstalk of Monolithic 3D Circuits Based on a 22 nm FD-SOI Technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

The Synergetic Effects of Total Ionizing Dose and High Temperature on 180 nm DSOI Technology.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021
SPICE Compact BJT, MOSFET, and JFET Models for ICs Simulation in the Wide Temperature Range (From -200 °C to +300 °C).
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Simulations of single event effects on the ferroelectric capacitor-based non-volatile SRAM design.
Sci. China Inf. Sci., 2021

2020
Performance Optimization of FD-SOI Hall Sensors Via 3D TCAD Simulations.
Sensors, 2020

Soft Error Reliability Evaluation of Nanoscale Logic Circuits in the Presence of Multiple Transient Faults.
J. Electron. Test., 2020

Simulation of Total Ionizing Dose (TID) Effects Mitigation Technique for 22 nm Fully-Depleted Silicon-on-Insulator (FDSOI) Transistor.
IEEE Access, 2020

2019
Total ionizing dose effects on graphene-based charge-trapping memory.
Sci. China Inf. Sci., 2019

Influences of the Source and Drain Resistance of the MOSFETs on the Single Event Upset Hardness of SRAM cells.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
A single event upset tolerant latch design.
Microelectron. Reliab., 2018

Process variation dependence of total ionizing dose effects in bulk nFinFETs.
Microelectron. Reliab., 2018

Constant voltage stress characterization of nFinFET transistor during total ionizing dose experiment.
Microelectron. Reliab., 2018

Total ionizing dose and single event effects of 1 Mb HfO<sub>2</sub>-based resistive-random-access memory.
Microelectron. Reliab., 2018

2017
Total ionizing dose effects and annealing behaviors of HfO<sub>2</sub>-based MOS capacitor.
Sci. China Inf. Sci., 2017

2012
A Digital Dual-State-Variable Predictive Controller for High Switching Frequency Buck Converter With Improved Σ-Δ DPWM.
IEEE Trans. Ind. Informatics, 2012

Low Power Digital Alternative to Analog Control of Step-Down Converter.
J. Low Power Electron., 2012

An FPGA prototype of current and voltage predictive controller for high switching frequency buck converter.
Proceedings of the 38th Annual Conference on IEEE Industrial Electronics Society, 2012


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