Bo Li
Orcid: 0000-0003-4905-2744Affiliations:
- Chinese Academy of Sciences, Institute of Microelectronics, Beijing, China
- INSA Lyon, Ampere Lab, Villeurbanne, France (PhD 2012)
According to our database1,
Bo Li authored at least 42 papers
between 2012 and 2026.
Collaborative distances:
Collaborative distances:
Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
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on orcid.org
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on ime.cas.cn
On csauthors.net:
Bibliography
2026
A 22.4-25.6-GHz Ping-Pong Sub-Sampling PLL Featuring Unified Supply Voltage Level and Balanced 2nd Harmonic Extraction.
IEEE J. Solid State Circuits, June, 2026
A 9-b 3-7.5-GHz 2.53-LSB-INL High-Linearity Phase Interpolator With CMOS-Signal-Targeted Calibration in 65-nm for High-Speed Data Links.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2026
High-Speed Floating Voltage Level Shifter With Self-Locked Noise Immunity for High-Side Gate Driver.
IEEE Trans. Very Large Scale Integr. Syst., March, 2026
A 5.4-GHz reference-sampling PLL-sub-sampling DLL cascaded frequency synthesizer achieving 85.7-fs RMS jitter in 65-nm CMOS.
Microelectron. J., 2026
TID-induced leakage-assisted degradation and failure mechanisms in cathode-short base-resistance-controlled thyristors.
Microelectron. J., 2026
Microelectron. J., 2026
25.10 A 65nm 0.066pJ/b Floating-Latch-Based True Random Number Generator Resilient to Power-Noise Injection Attacks.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
A 2-GHz 5.06-mW Phase Accumulator Employing Dynamic Regulation for High-Speed Direct Digital Frequency Synthesizers in 65-nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026
A D-Band Power Amplifier with A Novel Gain-Boosting Structure Achieving 15.8-dB Gain and 23.9-GHz Bandwidth in 65-nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026
2025
IEEE Trans. Circuits Syst. II Express Briefs, August, 2025
RIVL: A Low-Cost SoC Agile Development Platform for Multiple RISC-V Processors Design and Verification.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2025
Radiation Dose Detector of γ-Ray Based on Transient Nonequilibrium Body Potential Under Pseudo-MOSFET Configuration.
IEEE Trans. Instrum. Meas., 2025
A 600-V half-bridge gate drive circuit with high-speed and high-noise-immunity level shifter.
Microelectron. J., 2025
An Effective Method to Compensate for Testing Induced SBFET Degradation by Charging Deep-Level Interface Trap.
IEEE Access, 2025
2024
A nMOS-R Cross-Coupled Level Shifter With High dV/dt Noise Immunity for 600-V High-Voltage Gate Driver IC.
IEEE Trans. Very Large Scale Integr. Syst., November, 2024
A Novel Reliability-Enhanced Dual Over-Temperature Protection Circuit With Delayed Thermal Restart for Power ICs.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
Microelectron. J., 2024
A dual-mode buck converter with dynamic sawtooth voltage for wide input voltage range application.
IEICE Electron. Express, 2024
IEICE Electron. Express, 2024
A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter, and -76.5-dBc Reference Spur.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
2023
An on-chip integrated current sensor with high precision and large current range for smart power ICs.
Microelectron. J., April, 2023
Novel SenseFET structure for VDMOS with adopting body reverse bias technique to adjust the reference current ratio.
Microelectron. J., April, 2023
Microelectron. J., April, 2023
The Effects of $\gamma$ Radiation-Induced Trapped Charges on Single Event Transient in DSOI Technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2023
2022
Design and Experimentation of Inductorless Low-Pass NGD Integrated Circuit in 180-nm CMOS Technology.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Single Event Induced Crosstalk of Monolithic 3D Circuits Based on a 22 nm FD-SOI Technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
The Synergetic Effects of Total Ionizing Dose and High Temperature on 180 nm DSOI Technology.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
2021
SPICE Compact BJT, MOSFET, and JFET Models for ICs Simulation in the Wide Temperature Range (From -200 °C to +300 °C).
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Simulations of single event effects on the ferroelectric capacitor-based non-volatile SRAM design.
Sci. China Inf. Sci., 2021
2020
Sensors, 2020
Soft Error Reliability Evaluation of Nanoscale Logic Circuits in the Presence of Multiple Transient Faults.
J. Electron. Test., 2020
Simulation of Total Ionizing Dose (TID) Effects Mitigation Technique for 22 nm Fully-Depleted Silicon-on-Insulator (FDSOI) Transistor.
IEEE Access, 2020
2019
Sci. China Inf. Sci., 2019
Influences of the Source and Drain Resistance of the MOSFETs on the Single Event Upset Hardness of SRAM cells.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2018
Microelectron. Reliab., 2018
Constant voltage stress characterization of nFinFET transistor during total ionizing dose experiment.
Microelectron. Reliab., 2018
Total ionizing dose and single event effects of 1 Mb HfO<sub>2</sub>-based resistive-random-access memory.
Microelectron. Reliab., 2018
2017
Total ionizing dose effects and annealing behaviors of HfO<sub>2</sub>-based MOS capacitor.
Sci. China Inf. Sci., 2017
2012
A Digital Dual-State-Variable Predictive Controller for High Switching Frequency Buck Converter With Improved Σ-Δ DPWM.
IEEE Trans. Ind. Informatics, 2012
J. Low Power Electron., 2012
An FPGA prototype of current and voltage predictive controller for high switching frequency buck converter.
Proceedings of the 38th Annual Conference on IEEE Industrial Electronics Society, 2012