Wen Li

Orcid: 0000-0002-8346-2926

Affiliations:
  • Shanxi University, Taiyuan, China


According to our database1, Wen Li authored at least 12 papers between 2018 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2025
Functional Testing and Repair for ReRAM-Based Deep-Learning Accelerators.
IEEE Des. Test, June, 2025

NeuVSA: A Unified and Efficient Accelerator for Neural Vector Search.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2025

2024
CoMO-NAS: Core-Structures-Guided Multi-Objective Neural Architecture Search for Multi-Modal Classification.
Proceedings of the 32nd ACM International Conference on Multimedia, MM 2024, Melbourne, VIC, Australia, 28 October 2024, 2024

AGC: A Unified Architecture for Accelerating K-Nearest Neighbor Graph Construction in Vector Search.
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

2023
On-Line Fault Protection for ReRAM-Based Neural Networks.
IEEE Trans. Computers, February, 2023

Communication-aware Quantization for Deep Learning Inference Parallelization on Chiplet-based Accelerators.
Proceedings of the 29th IEEE International Conference on Parallel and Distributed Systems, 2023

Adversarial Testing: A Novel On-Line Testing Method for Deep Learning Processors.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023

2019
Leveraging Memory PUFs and PIM-based encryption to secure edge deep learning systems.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

RRAMedy: Protecting ReRAM-Based Neural Network from Permanent and Soft Faults During Its Lifetime.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019

P<sup>3</sup>M: a PIM-based neural network model protection scheme for deep learning accelerator.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Lightweight Timing Channel Protection for Shared DRAM Controller.
Proceedings of the IEEE International Test Conference, 2018

Leveraging DRAM Refresh to Protect the Memory Timing Channel of Cloud Chip Multi-processors.
Proceedings of the IEEE International Test Conference in Asia, 2018


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