Jie Zhang

Orcid: 0000-0002-6299-4683

Affiliations:
  • Korea Advanced Institute of Science and Technology, Computer Architecture and Memory System Lab, Daejeon, South Korea
  • Yonsei University, Computer Architecture and Memory Systems Lab, Seoul, South Korea (PhD 2020)
  • University of Texas at Dallas, TX, USA (former)


According to our database1, Jie Zhang authored at least 34 papers between 2014 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
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Article 
PhD thesis 
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Links

Online presence:

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Bibliography

2023
Intelligent SSD Firmware for Zero-Overhead Journaling.
IEEE Comput. Archit. Lett., 2023

BcBench: Exploring Throughput Processor Designs based on Blockchain Benchmarking.
Proceedings of the 38th ACM/SIGAPP Symposium on Applied Computing, 2023

Experience Sharing: Research-Oriented Computing Education in Peking University.
Proceedings of the ACM Turing Award Celebration Conference - China 2023, 2023

2022
Survey on storage-accelerator data movement.
CCF Trans. High Perform. Comput., December, 2022

2021
Ohm-GPU: Integrating New Optical Network and Heterogeneous Memory into GPU Multi-Processors.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

Revamping Storage Class Memory With Hardware Automated Memory-Over-Storage Solution.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

2020
Errata to "Exploring Fault-Tolerant Erasure Codes for Scalable All-Flash Array Clusters".
IEEE Trans. Parallel Distributed Syst., 2020

FastDrain: Removing Page Victimization Overheads in NVMe Storage Stack.
IEEE Comput. Archit. Lett., 2020

Data Direct I/O Characterization for Future I/O System Exploration.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020

ZnG: Architecting GPU Multi-Processors with New Flash for Scalable Data Analysis.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

DRAM-Less: Hardware Acceleration of Data Processing with New Memory.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

Scalable Parallel Flash Firmware for Many-core Architectures.
Proceedings of the 18th USENIX Conference on File and Storage Technologies, 2020

2019
Exploring Fault-Tolerant Erasure Codes for Scalable All-Flash Array Clusters.
IEEE Trans. Parallel Distributed Syst., 2019

Faster than Flash: An In-Depth Study of System Challenges for Emerging Ultra-Low Latency SSDs.
Proceedings of the IEEE International Symposium on Workload Characterization, 2019

FUSE: Fusing STT-MRAM into GPUs to Alleviate Off-Chip Memory Access Overheads.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

FlashGPU: Placing New Flash Next to GPU Cores.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
ReveNAND: A Fast-Drift-Aware Resilient 3D NAND Flash Design.
ACM Trans. Archit. Code Optim., 2018

Enabling Realistic Logical Device Interface and Driver for NVM Express Enabled Full System Simulations.
Int. J. Parallel Program., 2018

SimpleSSD: Modeling Solid State Drives for Holistic System Simulation.
IEEE Comput. Archit. Lett., 2018

FlashShare: Punching Through Server Storage Stack from Kernel to Firmware for Ultra-Low Latency SSDs.
Proceedings of the 13th USENIX Symposium on Operating Systems Design and Implementation, 2018

Amber*: Enabling Precise Full-System Simulation with Detailed Modeling of All SSD Resources.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

CIAO: Cache Interference-Aware Throughput-Oriented Architecture and Scheduling for GPUs.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium, 2018

Flashabacus: a self-governing flash-based accelerator for low-power systems.
Proceedings of the Thirteenth EuroSys Conference, 2018

2017
An In-Depth Performance Analysis of Many-Integrated Core for Communication Efficient Heterogeneous Computing.
Proceedings of the Network and Parallel Computing, 2017

TraceTracker: Hardware/software co-evaluation for large-scale I/O workload reconstruction.
Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017

Understanding system characteristics of online erasure coding on scalable, distributed and large-scale SSD array systems.
Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017

2016
ROSS: A Design of Read-Oriented STT-MRAM Storage for Energy-Efficient Non-Uniform Cache Architecture.
Proceedings of the 4th Workshop on Interactions of NVM/Flash with Operating Systems and Workloads, 2016

Couture: Tailoring STT-MRAM for Persistent Main Memory.
Proceedings of the 4th Workshop on Interactions of NVM/Flash with Operating Systems and Workloads, 2016

An in-depth study of next generation interface for emerging non-volatile memories.
Proceedings of the 5th Non-Volatile Memory Systems and Applications Symposium, 2016

DUANG: Fast and lightweight page migration in asymmetric memory systems.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

2015
OpenNVM: An open-sourced FPGA-based NVM controller for low level memory characterization.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

NVMMU: A Non-volatile Memory Management Unit for Heterogeneous GPU-SSD Architectures.
Proceedings of the 2015 International Conference on Parallel Architectures and Compilation, 2015

Integrating 3D Resistive Memory Cache into GPGPU for Energy-Efficient Data Processing.
Proceedings of the 2015 International Conference on Parallel Architectures and Compilation, 2015

2014
Power, Energy, and Thermal Considerations in SSD-Based I/O Acceleration.
Proceedings of the 6th USENIX Workshop on Hot Topics in Storage and File Systems, 2014


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