Kaiwei Zou
Orcid: 0000-0002-5319-3665
According to our database1,
Kaiwei Zou
authored at least 9 papers
between 2014 and 2023.
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Bibliography
2023
Pareto Frequency-Aware Power Side-Channel Countermeasure Exploration on CNN Systolic Array.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023
A Weight-Reload-Eliminated Compute-in-Memory Accelerator for 60 fps 4K Super-Resolution.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023
Communication-aware Quantization for Deep Learning Inference Parallelization on Chiplet-based Accelerators.
Proceedings of the 29th IEEE International Conference on Parallel and Distributed Systems, 2023
Proceedings of the 32nd IEEE Asian Test Symposium, 2023
2022
Bit-Aware Fault-Tolerant Hybrid Retraining and Remapping Schemes for RRAM-Based Computing-in-Memory Systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
CAP: Communication-Aware Automated Parallelization for Deep Learning Inference on CMP Architectures.
IEEE Trans. Computers, 2022
2019
Learn-to-Scale: Parallelizing Deep Learning Inference on Chip Multiprocessor Architecture.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
XORiM: A case of in-memory bit-comparator implementation and its performance implications.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2014
Proceedings of the Modern Advances in Applied Intelligence, 2014