William L. Lynch

According to our database, William L. Lynch authored at least 3 papers between 1992 and 1998.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

1998

64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency.

Raymond A. Heald, Ken Shin, Vinita Reddy, I-Feng Kao, Masood Khan, William L. Lynch, Gary Lauterbach, Joe Petolino

IEEE J. Solid State Circuits, 1998

Low Load Latency Through Sum-Addressed Memory (SAM).

William L. Lynch, Gary Lauterbach, Joseph I. Chamdani

Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998

1992

The effect of page allocation on caches.

William L. Lynch, Brian K. Bray, Michael J. Flynn

Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992