Ken Shin

According to our database1, Ken Shin authored at least 7 papers between 1995 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
23.1 20nm high-K metal-gate heterogeneous 64b quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2013
28nm high- metal-gate heterogeneous quad-core CPUs for high-performance and energy-efficient mobile application processor.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Scan-controlled pulse flip-flops for mobile application processors.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2000
A third-generation SPARC V9 64-b microprocessor.
IEEE J. Solid State Circuits, 2000

1998
64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency.
IEEE J. Solid State Circuits, 1998

1995
A 64-b microprocessor with multimedia support.
IEEE J. Solid State Circuits, November, 1995

A three dimensional register file for superscalar processors.
Proceedings of the 28th Annual Hawaii International Conference on System Sciences (HICSS-28), 1995


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