William Y. Chen

According to our database¹, William Y. Chen authored at least 21 papers between 1991 and 2000.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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On csauthors.net:

Bibliography

2000

The Intel IA-64 Compiler Code Generator.

[BibT_eX]

[DOI]

IEEE Micro, 2000

1998

IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors.

[BibT_eX]

[DOI]

Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

1995

Three Architecutral Models for Compiler-Controlled Speculative Execution.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1995

The Importance of Prepass Code Scheduling for Superscalar and Superpipelined Processors.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1995

1994

Profile-assisted instruction scheduling.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 1994

Dynamic Memory Disambiguation Using the Memory Conflict Buffer.

[BibT_eX]

[DOI]

Proceedings of the ASPLOS-VI Proceedings, 1994

1993

Sentinel Scheduling for VLIW and Superscalar Processors.

[BibT_eX]

[DOI]

Michael S. Schlansker

ACM Trans. Comput. Syst., 1993

The superblock: An effective technique for VLIW and superscalar compilation.

[BibT_eX]

[DOI]

J. Supercomput., 1993

The Effect of Code Expanding Optimizations on Instruction Cache Design.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1993

[BibT_eX]

[DOI]

Proceedings of the 20th Annual International Symposium on Computer Architecture, 1993

1992

Profile-guided Automatic Inline Expansion for C Programs.

[BibT_eX]

[DOI]

Softw. Pract. Exp., 1992

Compiler Code Transformations for Superscalar-Based High Performance Systems.

[BibT_eX]

[DOI]

Proceedings of the Proceedings Supercomputing '92, 1992

Effective compiler support for predicated execution using the hyperblock.

[BibT_eX]

[DOI]

Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992

An efficient architecture for loop based data preloading.

[BibT_eX]

[DOI]

Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992

Using Profile Information to Assist Advaced Compiler Optimization and Scheduling.

[BibT_eX]

[DOI]

Proceedings of the Languages and Compilers for Parallel Computing, 1992

Tolerating data access latency with register preloading.

[BibT_eX]

[DOI]

Proceedings of the 6th international conference on Supercomputing, 1992

Tolerating First Level Memory Access Latency in High-Performance Systems.

[BibT_eX]

William Y. Chen

Scott A. Mahlke

Wen-mei W. Hwu

Proceedings of the 1992 International Conference on Parallel Processing, 1992

Sentinel Scheduling for VLIW and Superscalar Processors.

[BibT_eX]

[DOI]

Michael S. Schlansker

Proceedings of the ASPLOS-V Proceedings, 1992

1991

Data Access Microarchitectures for Superscalar Processors with Compiler-Assisted Data Prefetching.

[BibT_eX]

[DOI]

Proceedings of the 24th Annual IEEE/ACM International Symposium on Microarchitecture, 1991

Comparing Static and Dynamic Code Scheduling for Multiple-Instruction-Issue Processors.

[BibT_eX]

[DOI]

Proceedings of the 24th Annual IEEE/ACM International Symposium on Microarchitecture, 1991

The Effect of Compiler Optimizations on Available Parallelism in Scalar Programs.

[BibT_eX]

Proceedings of the International Conference on Parallel Processing, 1991

William Y. Chen

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