Gerolf Hoflehner

According to our database1, Gerolf Hoflehner authored at least 10 papers between 2000 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2011
AstroLIT: enabling simulation-based microarchitecture comparison between Intel® and Transmeta designs.
Proceedings of the 8th Conference on Computing Frontiers, 2011

2010
Strategies for Predicate-Aware Register Allocation.
Proceedings of the Compiler Construction, 19th International Conference, 2010

2009
Performance Characterization of Itanium® 2-Based Montecito Processor.
Proceedings of the Computer Performance Evaluation and Benchmarking, 2009

2007
Comparative characterization of SPEC CPU2000 and CPU2006 on Itanium architecture.
Proceedings of the 2007 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, 2007

2004
Compiler Optimizations for Transaction Processing Workloads on Itanium® Linux Systems.
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004

2003
The compiler as a validation and evaluation tool.
Proceedings of the Compiler Optimization Meets Compiler Verification, 2003

Optimization for the Intel® Itanium ®Architectur Register Stack.
Proceedings of the 1st IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2003), 2003

2002
Post-Pass Binary Adaptation for Software-Based Speculative Precomputation.
Proceedings of the 2002 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 2002

Quantitative Evaluation of the Register Stack Engine and Optimizations for Future Itanium Processors.
Proceedings of the 6th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-6 2002), 2002

2000
The Intel IA-64 Compiler Code Generator.
IEEE Micro, 2000


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