Mike Schlansker

According to our database, Mike Schlansker authored at least 43 papers between 1973 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2017

Design Challenges for High Performance, Scalable NFV Interconnects.

Guyue Liu, K. K. Ramakrishnan, Mike Schlansker, Jean Tourrilhes, Timothy Wood

Proceedings of the Workshop on Kernel-Bypass Networks, 2017

2016

The 2014 MICRO Test of Time Award Winners: From 1978 to 1992.

Onur Mutlu, Rich Belgard, Nick Tredennick, Mike Schlansker

IEEE Micro, 2016

2015

Enabling Topological Flexibility for Data Centers Using OmniSwitch.

Yiting Xia, Mike Schlansker, T. S. Eugene Ng, Jean Tourrilhes

Proceedings of the 7th USENIX Workshop on Hot Topics in Cloud Computing, 2015

2013

Configurable optical interconnects for scalable datacenters.

Michael S. Schlansker, Michael R. T. Tan, Jean Tourrilhes, Jose Renato Santos, Shih-Yuan Wang

Proceedings of the 2013 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC), 2013

2012

CORONET: Fault tolerance for Software Defined Networks.

Hyojoon Kim, Mike Schlansker, Jose Renato Santos, Jean Tourrilhes, Yoshio Turner, Nick Feamster

Proceedings of the 20th IEEE International Conference on Network Protocols, 2012

2011

Cydra 5.

Michael S. Schlansker

Proceedings of the Encyclopedia of Parallel Computing, 2011

Routing Optimization for Ensemble Routing.

Wenfei Wu, Yoshio Turner, Mike Schlansker

Proceedings of the 2011 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), 2011

2010

Killer Fabrics for Scalable Datacenters.

Mike Schlansker, Jean Tourrilhes, Yoshio Turner, Jose Renato Santos

Proceedings of IEEE International Conference on Communications, 2010

Ensemble routing for datacenter networks.

Mike Schlansker, Yoshio Turner, Jean Tourrilhes, Alan Karp

Proceedings of the 2010 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2010

2009

Hash-based routing for scalable datacenters.

Mike Schlansker, Jean Tourrilhes, Yoshio Turner, Jose Renato Santos

Proceedings of the 2009 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2009

2007

High-performance ethernet-based communications for future multi-core processors.

Michael S. Schlansker, Nagabhushan Chitlur, Erwin Oertli, Paul M. Stillwell Jr., Linda Rankin, Dennis Bradford, Richard J. Carter, Jayaram Mudigonda, Nathan L. Binkert, Norman P. Jouppi

Proceedings of the ACM/IEEE Conference on High Performance Networking and Computing, 2007

2006

Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers.

Jack Sampson, Rubén González, Jean-Francois Collard, Norman P. Jouppi, Michael S. Schlansker, Brad Calder

Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

2005

Fast synchronization for chip multiprocessors.

Jack Sampson, Rubén González, Jean-Francois Collard, Norman P. Jouppi, Michael S. Schlansker

SIGARCH Comput. Archit. News, 2005

A Distributed Control Path Architecture for VLIW Processors.

Hongtao Zhong, Kevin Fan, Scott A. Mahlke, Michael S. Schlansker

Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT 2005), 2005

2003

In Memory of Bob Rau.

Michael S. Schlansker

Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003

2001

Bitwidth cognizant architecture synthesis of custom hardwareaccelerators.

Scott A. Mahlke, Rajiv A. Ravindran, Michael S. Schlansker, Robert Schreiber, Timothy Sherwood

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Compiling for EPIC architectures.

Vinod Kathail, Michael S. Schlansker, B. Ramakrishna Rau

Proc. IEEE, 2001

Guest Editors' Introduction.

Michael S. Schlansker, Chris J. Newburn

J. Instr. Level Parallelism, 2001

Embedded Computer Architecture and Automation.

B. Ramakrishna Rau, Michael S. Schlansker

Computer, 2001

ShiftQ: a bufferred interconnect for custom loop accelerators.

Shail Aditya, Michael S. Schlansker

Proceedings of the 2001 International Conference on Compilers, 2001

2000

EPIC: Explicititly Parallel Instruction Computing.

Michael S. Schlansker, B. Ramakrishna Rau

Computer, 2000

Embedded Computing: New Directions in Architecture and Automation.

B. Ramakrishna Rau, Michael S. Schlansker

Proceedings of the High Performance Computing, 2000

1999

Control CPR: A Branch Height Reduction Optimization for EPIC Architectures.

Michael S. Schlansker, Scott A. Mahlke, Richard Johnson

Proceedings of the 1999 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 1999

1997

Techniques for critical path reduction of scalar programs.

Michael S. Schlansker, Vinod Kathail

Int. J. Parallel Program., 1997

Compilers for Instruction-Level Parallelism.

Michael S. Schlansker, Thomas M. Conte, James C. Dehnert, Kemal Ebcioglu, Jesse Zhixi Fang, Carol L. Thompson

Computer, 1997

Challenges to Combining General-Purpose and Multimedia Processors.

Thomas M. Conte, Pradeep K. Dubey, Matthew D. Jennings, Ruby B. Lee, Alex Peleg, Salliah Rathnam, Michael S. Schlansker, Peter Song, Andrew Wolfe

Computer, 1997

1996

Parallelization of Control Recurrences for ILP Processors.

Michael S. Schlansker, Vinod Kathail, Sadun Anik

Int. J. Parallel Program., 1996

Analysis Techniques for Predicated Code.

Richard Johnson, Michael S. Schlansker

Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, 1996

Global Predicate Analysis and Its Application to Register Allocation.

David M. Gillies, Roy Dz-Ching Ju, Richard Johnson, Michael S. Schlansker

Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, 1996

Profile-driven Instruction Level Parallel Scheduling with Application to Super Blocks.

Chandra Chekuri, Richard Johnson, Rajeev Motwani, B. Natarajan, B. Ramakrishna Rau, Michael S. Schlansker

Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, 1996

1995

Critical path reduction for scalar programs.

Michael S. Schlansker, Vinod Kathail

Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29, 1995

Spill-free parallel scheduling of basic blocks.

B. Natarajan, Michael S. Schlansker

Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29, 1995

1994

Height reduction of control recurrences for ILP processors.

Michael S. Schlansker, Vinod Kathail, Sadun Anik

Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30, 1994

1993

Sentinel Scheduling for VLIW and Superscalar Processors.

Scott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker

ACM Trans. Comput. Syst., 1993

Acceleration of First and Higher Order Recurrences on Processors with Instruction Level Parallelism.

Michael S. Schlansker, Vinod Kathail

Proceedings of the Languages and Compilers for Parallel Computing, 1993

1992

Register Allocation for Software Pipelined Loops.

B. Ramakrishna Rau, Meng Lee, Parthasarathy P. Tirumalai, Michael S. Schlansker

Proceedings of the ACM SIGPLAN'92 Conference on Programming Language Design and Implementation (PLDI), 1992

Code generation schema for modulo scheduled loops.

B. Ramakrishna Rau, Michael S. Schlansker, Parthasarathy P. Tirumalai

Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992

Sentinel Scheduling for VLIW and Superscalar Processors.

Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker

Proceedings of the ASPLOS-V Proceedings, 1992

1991

Parallelization of WHILE loops on pipelined architectures.

Parthasarathy P. Tirumalai, Meng Lee, Michael S. Schlansker

J. Supercomput., 1991

1990

Parallelization of loops with exits on pipelined architectures.

Parthasarathy P. Tirumalai, Meng Lee, Michael S. Schlansker

Proceedings of the Proceedings Supercomputing '90, New York, NY, USA, November 12-16, 1990, 1990

1989

The Cydram 5 Stride-Insensitive Memory System.

B. Ramakrishna Rau, Michael S. Schlansker, David W. L. Yen

Proceedings of the International Conference on Parallel Processing, 1989

1982

Systematically derived instruction sets for high-level language support.

Pradip Bose, B. Ramakrishna Rau, Michael S. Schlansker

Proceedings of the 20th Annual Southeast Regional Conference, 1982

1973

A microprogramming language for the B-1726.

David J. DeWitt, Michael S. Schlansker, Daniel E. Atkins

Proceedings of the Conference record of the 6th annual workshop on Microprogramming, 1973