Xi Chen

Orcid: 0009-0007-5111-6571

Affiliations:
  • Northwestern University, Evanston, IL, USA


According to our database1, Xi Chen authored at least 10 papers between 2021 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Online presence:

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Bibliography

2025
A 65-nm Proactive Power Management Technique With Real-Time Machine Learning Engine for Droop Prediction and Mitigation on Microprocessors.
IEEE J. Solid State Circuits, June, 2025

Mobile-PBR: A 28-nm Energy-Efficient Rendering Processor for Photorealistic Augmented Reality With Inverse Rendering and Background Clustering.
IEEE J. Solid State Circuits, January, 2025

2024
LLM-MARK: A Computing Framework on Efficient Watermarking of Large Language Models for Authentic Use of Generative AI at Local Devices.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023
Human Activity Recognition SoC for AR/VR with Integrated Neural Sensing, AI Classifier and Chained Infrared Communication for Multi-chip Collaboration.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A General-Purpose Compute-in-Memory Processor Combining CPU and Deep Learning with Elevated CPU Efficiency and Enhanced Data Locality.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Proactive Power Regulation with Real-time Prediction and Fast Response Guardband for Fine-grained Dynamic Voltage Droop Mitigation on Digital SoCs.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Development of Tropical Algebraic Accelerator with Energy Efficient Time-Domain Computing for Combinatorial Optimization and Machine Learning.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

A 65nm Fully-integrated Fast-switching Buck Converter with Resonant Gate Drive and Automatic Tracking.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022
A 65nm Implantable Gesture Classification SoC for Rehabilitation with Enhanced Data Compression and Encoding for Robust Neural Network Operation Under Wireless Power Condition.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2021
15.3 A 65nm 3T Dynamic Analog RAM-Based Computing-in-Memory Macro and CNN Accelerator with Retention Enhancement, Adaptive Analog Sparsity and 44TOPS/W System Energy Efficiency.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021


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