Tianyu Jia
Orcid: 0000-0001-6645-509X
According to our database1,
Tianyu Jia
authored at least 48 papers
between 2015 and 2024.
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Bibliography
2024
Silent Data Corruption in Robot Operating System: A Case for End-to-End System-Level Fault Analysis Using Autonomous UAVs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024
IEEE J. Biomed. Health Informatics, February, 2024
14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
30.2 A 22nm 0.26nW/Synapse Spike-Driven Spiking Neural Network Processing Unit Using Time-Step-First Dataflow and Sparsity-Adaptive In-Memory Computing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
IEEE Des. Test, December, 2023
Sci. China Inf. Sci., October, 2023
Trireme: Exploration of Hierarchical Multi-level Parallelism for Hardware Acceleration.
ACM Trans. Embed. Comput. Syst., 2023
Spatio-Temporal Evolution of Inland Lakes and Their Relationship with Hydro-Meteorological Factors in Horqin Sandy Land, China.
Remote. Sens., 2023
A 12nm 18.1TFLOPs/W Sparse Transformer Processor with Entropy-Based Early Exit, Mixed-Precision Predication and Fine-Grained Power Management.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 22nm Delta-Sigma Computing-In-Memory (Δ∑CIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
DCIM-3DRec: A 3D Reconstruction Accelerator with Digital Computing-in-Memory and Octree-Based Scheduler.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
MAVFI: An End-to-End Fault Analysis Framework with Anomaly Detection and Recovery for Micro Aerial Vehicles.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
A Model-Specific End-to-End Design Methodology for Resource-Constrained TinyML Hardware.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
A A 22nm 0.43pJ/SOP Sparsity-Aware In-Memory Neuromorphic Computing System with Hybrid Spiking and Artificial Neural Network and Configurable Topology.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A 65nm Fully-integrated Fast-switching Buck Converter with Resonant Gate Drive and Automatic Tracking.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
Trireme: Exploring Hierarchical Multi-Level Parallelism for Domain Specific Hardware Acceleration.
CoRR, 2022
A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
A Differentiable Neural Computer for Logic Reasoning with Scalable Near-Memory Computing and Sparsity Based Enhancement.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
FRL-FI: Transient Fault Analysis for Federated Reinforcement Learning-Based Navigation Systems.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
OMU: A Probabilistic 3D Occupancy Mapping Accelerator for Real-time OctoMap at the Edge.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
A Dynamic Timing Enhanced DNN Accelerator With Compute-Adaptive Elastic Clock Chain Technique.
IEEE J. Solid State Circuits, 2021
MAVFI: An End-to-End Fault Analysis Framework with Anomaly Detection and Recovery for Micro Aerial Vehicles.
CoRR, 2021
EdgeBERT: Sentence-Level Energy Optimizations for Latency-Aware Multi-Task NLP Inference.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
Proceedings of the 43rd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
FlexACC: A Programmable Accelerator with Application-Specific ISA for Flexible Deep Neural Network Inference.
Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021
2020
An Adaptive Clock Scheme Exploiting Instruction-Based Dynamic Timing Slack for a GPGPU Architecture.
IEEE J. Solid State Circuits, 2020
Small-Dimension Feature Matrix Construction Method for Decoding Repetitive Finger Movements From Electroencephalogram Signals.
IEEE Access, 2020
NCPU: An Embedded Neural CPU Architecture on Resource-Constrained Low Power Devices for Real-time End-to-End Performance.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
31.3 A Compute-Adaptive Elastic Clock-Chain Technique with Dynamic Timing Enhancement for 2D PE-Array-Based Accelerators.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
An Instruction-Driven Adaptive Clock Management Through Dynamic Phase Scaling and Compiler Assistance for a Low Power Microprocessor.
IEEE J. Solid State Circuits, 2019
A 48 V Input 0.75 V Output DC-DC Converter Power Block for HPC Systems and Datacenters (invited paper).
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
An Adaptive Clock Management Scheme Exploiting Instruction-Based Dynamic Timing Slack for a General-Purpose Graphics Processor Unit with Deep Pipeline and Out-of-Order Execution.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Words in Kitchen: An Instance of Leveraging Virtual Reality Technology to Learn Vocabulary.
Proceedings of the IEEE International Symposium on Mixed and Augmented Reality, 2019
2018
A Fully Integrated Buck Regulator With 2-GHz Resonant Switching for Low-Power Applications.
IEEE J. Solid State Circuits, 2018
Holistic Energy Management with μProcessor Co-Optimization in Fully Integrated Battery-Less IoTs.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018
Design and optimization of edge computing distributed neural processor for biomedical rehabilitation with sensor fusion.
Proceedings of the International Conference on Computer-Aided Design, 2018
An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
Compiler-guided instruction-level clock scheduling for timing speculative processors.
Proceedings of the 55th Annual Design Automation Conference, 2018
A Fully-integrated LC-Oscillator Based Buck Regulator with Autonomous Resonant Switching for Low-Power Applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
(Invited) Software-guided greybox design methodology with integrated power and clock management.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Greybox Design Methodology: A Program Driven Hardware Co-optimization with Ultra-Dynamic Clock Management.
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
Exploration of associative power management with instruction governed operation for ultra-low power design.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the 2016 IEEE International Congress on Big Data, San Francisco, CA, USA, June 27, 2016
2015
Proceedings of the ESSCIRC Conference 2015, 2015