Xi Wang

Orcid: 0000-0002-1998-6733

Affiliations:
  • Texas Tech University, Lubbock, Texas, USA


According to our database1, Xi Wang authored at least 20 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
A 0.61-μW Fully Integrated Keyword-Spotting ASIC With Real-Point Serial FFT-Based MFCC and Temporal Depthwise Separable CNN.
IEEE J. Solid State Circuits, March, 2024

2021
HAM: Hotspot-Aware Manager for Improving Communications With 3D-Stacked Memory.
IEEE Trans. Computers, 2021

CircusTent: A Tool for Measuring the Performance of Atomic Memory Operations on Emerging Architectures.
Proceedings of the OpenSHMEM and Related Technologies. OpenSHMEM in the Era of Exascale and Smart Networks, 2021

xBGAS: A Global Address Space Extension on RISC-V for High Performance Computing.
Proceedings of the 35th IEEE International Parallel and Distributed Processing Symposium, 2021

DMM-GAPBS: Adapting the GAP Benchmark Suite to a Distributed Memory Model.
Proceedings of the 2021 IEEE High Performance Extreme Computing Conference, 2021

2020
Toward a Microarchitecture for Efficient Execution of Irregular Applications.
ACM Trans. Parallel Comput., 2020

CircusTent: A Benchmark Suite for Atomic Memory Operations.
Proceedings of the MEMSYS 2020: The International Symposium on Memory Systems, 2020

PAC: Paged Adaptive Coalescer for 3D-Stacked Memory.
Proceedings of the HPDC '20: The 29th International Symposium on High-Performance Parallel and Distributed Computing, 2020

Remote Atomic Extension (RAE) for Scalable High Performance Computing.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
PIMS: a lightweight processing-in-memory accelerator for stencil computations.
Proceedings of the International Symposium on Memory Systems, 2019

Collective Communication for the RISC-V xBGAS ISA Extension.
Proceedings of the 48th International Conference on Parallel Processing, 2019

MAC: Memory Access Coalescer for 3D-Stacked Memory.
Proceedings of the 48th International Conference on Parallel Processing, 2019

POSTER: Memory Hotspot Optimization for Data-Intensive Applications.
Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019

2018
xBGAS: Toward a RISC-V ISA Extension for Global, Scalable Shared Memory.
Proceedings of the Workshop on Memory Centric High Performance Computing, 2018

Memory Coalescing for Hybrid Memory Cube.
Proceedings of the 47th International Conference on Parallel Processing, 2018

GoblinCore-64: A RISC-V Based Architecture for Data Intensive Computing.
Proceedings of the 2018 IEEE High Performance Extreme Computing Conference, 2018

2017
Pressure-Driven Hardware Managed Thread Concurrency for Irregular Applications.
Proceedings of the Seventh Workshop on Irregular Applications: Architectures and Algorithms, 2017

OpenMP Memkind: An Extension for Heterogeneous Physical Memories.
Proceedings of the 46th International Conference on Parallel Processing Workshops, 2017

OpenSoC system architect: An open toolkit for building soft-cores on FPGAs.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016
Concurrent Dynamic Memory Coalescing on GoblinCore-64 Architecture.
Proceedings of the Second International Symposium on Memory Systems, 2016


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