Jieru Zhao

According to our database, Jieru Zhao authored at least 30 papers between 2017 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

HGS-Mapping: Online Dense Mapping Using Hybrid Gaussian Representation in Urban Scenes.

Ke Wu, Kaizhao Zhang, Zhiwei Zhang, Shanshuai Yuan, Muer Tie, Julong Wei, Zijun Xu, Jieru Zhao, Zhongxue Gan, Wenchao Ding

CoRR, 2024

Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs.

Mingzhe Gao, Jieru Zhao, Zhe Lin, Minyi Guo

CoRR, 2024

An Optimizing Framework on MLIR for Efficient FPGA-based Accelerator Generation.

Weichuang Zhang, Jieru Zhao, Guan Shen, Quan Chen, Chen Chen, Minyi Guo

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

Swift-Mapping: Online Neural Implicit Dense Mapping in Urban Scenes.

Ke Wu, Kaizhao Zhang, Mingzhe Gao, Jieru Zhao, Zhongxue Gan, Wenchao Ding

Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024

2023

HL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLS.

Zhe Lin, Tingyuan Liang, Jieru Zhao, Sharad Sinha, Wei Zhang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

FPGA sharing in the cloud: a comprehensive analysis.

Jinyang Guo, Lu Zhang, José Romero Hung, Chao Li, Jieru Zhao, Minyi Guo

Frontiers Comput. Sci., October, 2023

PAC: Preference-Aware Co-location Scheduling on Heterogeneous NUMA Architectures To Improve Resource Utilization.

Pu Pang, Yaoxuan Li, Bo Liu, Quan Chen, Zhou Yu, Zhibin Yu, Deze Zeng, Jingwen Leng, Jieru Zhao, Minyi Guo

Proceedings of the 37th International Conference on Supercomputing, 2023

FlowMap: Path Generation for Automated Vehicles in Open Space Using Traffic Flow.

Wenchao Ding, Jieru Zhao, Yubin Chu, Haihui Huang, Tong Qin, Chunjing Xu, Yuxiang Guan, Zhongxue Gan

Proceedings of the IEEE International Conference on Robotics and Automation, 2023

Skadi: Building a Distributed Runtime for Data Systems in Disaggregated Data Centers.

Cunchen Hu, Chenxi Wang, Sa Wang, Ninghui Sun, Yungang Bao, Jieru Zhao, Sanidhya Kashyap, Pengfei Zuo, Xusheng Chen, Liangliang Xu, Qin Zhang, Hao Feng, Yizhou Shan

Proceedings of the 19th Workshop on Hot Topics in Operating Systems, 2023

SSiMD: Supporting Six Signed Multiplications in a DSP Block for Low-Precision CNN on FPGAs.

Qi Liu, Mo Sun, Jie Sun, Liqiang Lu, Jieru Zhao, Zeke Wang

Proceedings of the International Conference on Field Programmable Technology, 2023

SpMMPlu: A Compiler Plug-in with Sparse IR for Efficient Sparse Matrix Multiplication.

Tao Yang, Yiyuan Zhou, Qidong Tang, Feng Xu, Hui Ma, Jieru Zhao, Li Jiang

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

MARS: Exploiting Multi-Level Parallelism for DNN Workloads on Adaptive Multi-Accelerator Systems.

Guan Shen, Jieru Zhao, Zeke Wang, Zhe Lin, Wenchao Ding, Chentao Wu, Quan Chen, Minyi Guo

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

DataFlower: Exploiting the Data-flow Paradigm for Serverless Workflow Orchestration.

Zijun Li, Chuhao Xu, Quan Chen, Jieru Zhao, Chen Chen, Minyi Guo

Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2022

AMF-Placer 2.0: Open Source Timing-driven Analytical Mixed-size Placer for Large-scale Heterogeneous FPGA.

Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang

CoRR, 2022

CSC: Collaborative System Configuration for I/O-Intensive Applications in Multi-Tenant Clouds.

Haowei Huang, Pu Pang, Quan Chen, Jieru Zhao, Wenli Zheng, Minyi Guo

Proceedings of the 2022 IEEE International Parallel and Distributed Processing Symposium, 2022

PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs.

Zhe Lin, Zike Yuan, Jieru Zhao, Wei Zhang, Hui Wang, Yonghong Tian

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

SALO: an efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences.

Guan Shen, Jieru Zhao, Quan Chen, Jingwen Leng, Chao Li, Minyi Guo

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Characterizing and orchestrating VM reservation in geo-distributed clouds to improve the resource efficiency.

Jiuchen Shi, Kaihua Fu, Quan Chen, Changpeng Yang, Pengfei Huang, Mosong Zhou, Jieru Zhao, Chen Chen, Minyi Guo

Proceedings of the 13th Symposium on Cloud Computing, SoCC 2022, 2022

2021

Enable simultaneous DNN services based on deterministic operator overlap and precise latency prediction.

Weihao Cui, Han Zhao, Quan Chen, Ningxin Zheng, Jingwen Leng, Jieru Zhao, Zhuo Song, Tao Ma, Yong Yang, Chao Li, Minyi Guo

Proceedings of the International Conference for High Performance Computing, 2021

Exploiting Intra-SM Parallelism in GPUs via Persistent and Elastic Blocks.

Han Zhao, Weihao Cui, Quan Chen, Jieru Zhao, Jingwen Leng, Minyi Guo

Proceedings of the 39th IEEE International Conference on Computer Design, 2021

AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGA.

Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

2020

Performance Modeling and Directives Optimization for High-Level Synthesis on FPGA.

Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang, Bingsheng He

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications.

Jieru Zhao, Tingyuan Liang, Liang Feng, Wenchao Ding, Sharad Sinha, Wei Zhang, Shaojie Shen

Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis.

Zhe Lin, Jieru Zhao, Sharad Sinha, Wei Zhang

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019

Hi-ClockFlow: Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis.

Tingyuan Liang, Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang

Proceedings of the International Conference on Computer-Aided Design, 2019

A Hybrid Data-Consistent Framework for Link-Aware AccessManagement in Emerging CPU-FPGA Platforms.

Liang Feng, Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis.

Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

LAMA: Link-Aware Hybrid Management for Memory Accesses in Emerging CPU-FPGA Platforms.

Liang Feng, Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

Hi-DMM: High-Performance Dynamic Memory Management in High-Level Synthesis.

Tingyuan Liang, Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2017

COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications.

Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang, Bingsheng He

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017