Xiangxun Zhan

According to our database, Xiangxun Zhan authored at least 4 papers between 2023 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

A 0.068mm² 8.5-to-12.7GHz Complementary Dual-Core VCO with Auto-2^nd-Harmonic-Tracking Technique Achieving 202.7dBc/Hz Peak FoMT and 0.9dB-FoM Variation at a 1MHz Offset in a 39.6% Tuning Range.

Xincheng Du, Xiangxun Zhan, Tincheng Ou, Zaize Chen, Jinge Li, Haoran Li, Zhizhan Yang, Zhuo Xu, Pui-In Mak, Rui Paulo Martins, Jun Yin

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

2025

Analysis and Design of a Type-II Reference-Sampling PLL Using Gain-Boosting Phase Detector With Sampling Capacitor Reduction.

Tailong Xu, Haoran Li, Xi Meng, Xiangxun Zhan, Yatao Peng, Jun Yin, Shiheng Yang, Chao Fan, Zhixiang Huang, Rui Paulo Martins, Pui-In Mak

IEEE Trans. Circuits Syst. II Express Briefs, March, 2025

A Series-LC-Assisted Oscillator Achieving -140.2 dBc/Hz Phase Noise and 187.5 dBc/Hz FoM at 10 MHz Offset From 10.7 GHz.

Xiangxun Zhan, Jun Yin, Rui Paulo Martins, Pui-In Mak

IEEE Trans. Circuits Syst. II Express Briefs, February, 2025

2023

A 22.4-to-26.8GHz Dual-Path-Synchronized Quad-Core Oscillator Achieving -138dBc/Hz PN and 193.3dBc/Hz FoM at 10MHz Offset from 25.8GHz.

Xiangxun Zhan, Jun Yin, Pui-In Mak, Rui Paulo Martins

Proceedings of the IEEE International Solid- State Circuits Conference, 2023