Haoran Li

According to our database, Haoran Li authored at least 9 papers between 2021 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

A Low-Jitter mm-Wave Fractional-N Sub-Sampling PLL Using a Polarity-Reversible SSPD for DTC Range Reduction.

Haoran Li, Jinge Li, Xueying Jiang, Xi Meng, Pui-In Mak, Rui Paulo Martins, Jun Yin

IEEE J. Solid State Circuits, June, 2026

A 0.068mm² 8.5-to-12.7GHz Complementary Dual-Core VCO with Auto-2^nd-Harmonic-Tracking Technique Achieving 202.7dBc/Hz Peak FoMT and 0.9dB-FoM Variation at a 1MHz Offset in a 39.6% Tuning Range.

Xincheng Du, Xiangxun Zhan, Tincheng Ou, Zaize Chen, Jinge Li, Haoran Li, Zhizhan Yang, Zhuo Xu, Pui-In Mak, Rui Paulo Martins, Jun Yin

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

A 0.039mm² Temperature-Robust 7.2GHz Fractional-N RO-PLL Achieving 257.9fsrms Jitter and -255.5dB FoMN.

Haoran Li, Jinge Li, Shangmin Yu, Xiaoqi Lin, Xueying Jiang, Xi Meng, Pui-In Mak, Rui Paulo Martins, Jun Yin

Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

2025

Analysis and Design of a Type-II Reference-Sampling PLL Using Gain-Boosting Phase Detector With Sampling Capacitor Reduction.

Tailong Xu, Haoran Li, Xi Meng, Xiangxun Zhan, Yatao Peng, Jun Yin, Shiheng Yang, Chao Fan, Zhixiang Huang, Rui Paulo Martins, Pui-In Mak

IEEE Trans. Circuits Syst. II Express Briefs, March, 2025

19.7 A 27GHz Fractional-N Sub-Sampling PLL Achieving 57.9fs_rms Jitter, -249.7dB FoM, and 1.98µS Locking Time Using Polarity-Reversible SSPD.

Haoran Li, Jinge Li, Xueying Jiang, Xi Meng, Jun Yin, Rui Paulo Martins, Pui-In Mak

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2024

A 23.2-to-26-GHz Low-Jitter Fast-Locking Sub-Sampling PLL Based on a Function-Reused VCO-Buffer and a Type-I FLL With Rapid Phase Alignment.

Haoran Li, Tailong Xu, Xi Meng, Jun Yin, Rui Paulo Martins, Pui-In Mak

IEEE J. Solid State Circuits, December, 2024

10.9 A 23.2-to-26GHz Sub-Sampling PLL Achieving 48.3fsrms Jitter, -253.5dB FoMJ, and 0.55μs Locking Time Based on a Function-Reused VCO-Buffer and a Type-I FLL with Rapid Phase Alignment.

Haoran Li, Tailong Xu, Xi Meng, Jun Yin, Rui Paulo Martins, Pui-In Mak

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023

Analysis and Design of a 15.2-to-18.2-GHz Inverse-Class-F VCO With a Balanced Dual-Core Topology Suppressing the Flicker Noise Upconversion.

Xi Meng, Haoran Li, Peng Chen, Jun Yin, Pui-In Mak, Rui Paulo Martins

IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

2021

A 15.2-to-18.2GHz Balanced Dual-Core Inverse-Class-F VCO with Q-Enhanced 2^nd-Harmonic Resonance Achieving 187-to-188.1dBc/Hz FoM in 28nm CMOS.

Xi Meng, Junqi Guo, Haoran Li, Jun Yin, Pui-In Mak, Rui Paulo Martins

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021