Xiangyu Zhang

Orcid: 0000-0003-3716-4722

Affiliations:
  • ShanghaiTech University, School of Information Science and Technology, China
  • Hiroshima University, Graduate School of Engineering, Japan (PhD 2019)


According to our database1, Xiangyu Zhang authored at least 23 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
FPGA Accelerator for Human Activity Recognition Based on Radar.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

2023
An Efficient Frequency Domain Vision Pipeline From RAW Images to Backend Tasks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Image Frequency Separation Residual Network for End-to-end RAW to RGB Mapping.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022
A Raw Image-Based End-to-End Object Detection Accelerator Using HOG Features.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A Block PatchMatch-Based Energy-Resource Efficient Stereo Matching Processor on FPGA.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

An End-to-end Computer Vision System Architecture.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A 39pJ/label 1920x1080 165.7 FPS Block PatchMatch Based Stereo Matching Processor on FPGA.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

FPGA Accelerator for Radar-Based Human Activity Recognition.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021
Spatial Non-Maximum Suppression for Object Detection using Correlation and Dynamic Thresholds.
Proceedings of the 18th International SoC Design Conference, 2021

Stereo Point Cloud Refinement for 3D Object Detection.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021

Robust Multi-Source Direction of Arrival Estimation Using a Single Acoustic Vector Sensor.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021

Motion Assisted Video-based Stereo Matching.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021

2019
Energy-Efficient Hardware Implementation of Road-Lane Detection Based on Hough Transform with Parallelized Voting Procedure and Local Maximum Algorithm.
IEICE Trans. Inf. Syst., 2019

A Hardware-Efficient Recognition Accelerator Using Haar-Like Feature and SVM Classifier.
IEEE Access, 2019

2018
Resource-Efficient Object-Recognition Coprocessor With Parallel Processing of Multiple Scan Windows in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2018

A Hardware Architecture for Cell-Based Feature-Extraction and Classification Using Dual-Feature Space.
IEEE Trans. Circuits Syst. Video Technol., 2018

A Modular and Reconfigurable Pipeline Architecture for Learning Vector Quantization.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

2017
Real-Time Straight-Line Detection for XGA-Size Videos by Hough Transform with Parallelized Voting Procedures.
Sensors, 2017

A Vector-Quantization Compression Circuit With On-Chip Learning Ability for High-Speed Image Sensor.
IEEE Access, 2017

Object-recognition VLSI for pedestrian detection in automotive applications.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
A Memory-Based Modular Architecture for SOM and LVQ with Dynamic Configuration.
IEEE Trans. Multi Scale Comput. Syst., 2016

Dynamically reconfigurable system for LVQ-based on-chip learning and recognition.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Pixel-based pipeline hardware architecture for high-performance Haar-like feature extraction.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016


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